International Business Machines Corporation

Joseph J Van Horn

George Frederick Walker

Claude Louis Bertin

William R Tonti

Roger R Schmidt

Sampath Purushothaman

Michael A Gaynes

Kevin Shawn Petrarca

Mark Vincent Pierson

Richard Paul Volant

Alfred Viehbeck

Carlos Juan Sambucetti

Erik L Hedberg

Anilkumar Chinuprasad Bhatt

Charles Hampton Perry

Dennis R Barringer

David Lewis Gardell

David Andrew Lewis

Jerzy Maria Zalesinski

William E Bernier

John Harold Magerlein

Paul A Totta

Wade H White

Dennis R Conti

Paul M Gaschke

Samuel McKnight

James M Crafts

Mark R LaForce

Nikhil Mohan Murdeshwar

Susan J LaMaire

Jer-Ming Yang

Yuk L Tsang

Clarence S Long

Timothy A Redmond

Gavin T Mills

Jeffrey A Haley

Kathleen S Ginn

Peter E Freiermuth

Thomas W Bachelder

A system for testing a collection of device chips by temporarily attaching them to a carrier having a plurality of receptacles with microdendritic features; the receptacles matching with and pushed in contact with a matching set of contact pads on the device chips; said carrier additionally having test pads connected to the receptacles through interconnect wiring. The system allows connecting the chips together and testing the collection as a whole by probing the test pads on the carrier. Burn-in of the collection of chips can also be performed on the temporary carrier, which is reusable.

Temporary device attach structure for test and burn in of microjoint interconnects and method for fabricating the same

An apparatus for simultaneously testing or burning in a large number of the integrated circuit chips on a product wafer includes probes mounted on a first board and tester chips mounted on a second board, there being electrical connectors connecting the two boards. The tester chips are for distributing power to the product chips or for testing the product chips. The probes and thin film wiring to which they are attached are personalized for the pad footprint of the particular wafer being probed. The base of the first board and the second board both remain the same for all wafers in a product family. The use of two boards provides that the tester chip is kept at a substantially lower temperature than the product chips during burning to extend the lifetime of tester chips. A gap can be used as thermal insulation between the boards, and the gap sealed and evacuated for further thermal insulation. Evacuation also provides atmospheric pressure augmentation of contact for connection between boards and contact to wafer. Probes for parallel testing of chips are arranged in crescent shaped stripes to significantly increase tester throughput as compared with probes arranged in an area array.

Segmented architecture for wafer test and burn-in

Selective electrical connections between an electronic component and a test substrate are made using an electrical conductive material. The conductive material of the present invention is a dissolvable material, allowing for rework and repair of a wafer at the wafer-level, and retesting at the wafer-level. In addition, the conductive material may also be used in a permanent package, since the conductive material of the present invention provides complete electrical conductivity and connection between the electronic component and the substrate.

Selective wafer-level testing and burn-in

The described invention is directed to microwave methods for burning-in, electrical stressing, thermal stressing and reducing rectifying junction leakage current in fully processed semiconductor chips individually and at wafer level, as well as burning in and stressing semiconductor chip packaging substrates and the combination of a semiconductor chip mounted onto a semiconductor chip packaging substrate. Microwaves burn-in devices in a substantially shorter period of time than conventional burn-in techniques and avoid the need for special workpiece holders which are required by conventional stress and burn-in techniques. Additionally, microwave methods are described for reducing the leakage current of recitfying junctions, such as PN junctions and Schottky barrier diode junctions of semiconductor devices on fully processed semiconductor chips and wafers.

Method and apparatus for stressing, burning in and reducing leakage

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Underhill, VT, United States of America

Joseph J Van Horn