Motorola Corporation

Freescale Semiconductor,inc.

University of Notre Dame Du Lac

Everspin Technologies, Inc.

Other

Joseph J Nahas

Thomas Andre

Chitra K Subramanian

Bradley J Garni

Mark A Durlam

Brad John Garni

Nicholas David Rizzo

Bradley Neal Engel

Halbert S Lin

Saied N Tehrani

Behnam Sedighi

Mark F Deherrera

Michael Niemier

Gregory W Grynkewich

Brian R Butcher

Mark DeHerrera

Xiaobo Sharon Hu

Eric Johan Salter

X Sharon Hu

Clarance J Tracy

William Luther Martino, Jr

An electrical circuit is disclosed that comprises plurality of tunneling field-effect transistors (TFETs) arranged in a diffusion network matrix having a plurality of nodes wherein, for each of the TFETs that is not on an end of the matrix, a drain of the TFET is electrically coupled with the source of at least one of the other TFETs at a node of the matrix and a source of the TFET is electrically coupled with the drain of at least one of the other TFETs at another node of the matrix. The electrical circuit further comprises a plurality of capacitors, wherein a respective one of the plurality of capacitors is electrically coupled with each node that includes the source of at least one TFET and the drain of at least one TFET. The TFETs may be symmetrical graphene-insulator-graphene field-effect transistors (SymFETs), for example.

Systems and methods for filtering and computation using tunneling transistors

A Boolean gate includes at least one symmetric tunneling field-effect transistor (SymFET) for low-power information processing. SymFETs are ideal for applications that demand low power and have moderate speed requirements, and demonstrate better dynamic energy efficiency than CMOS circuits. Negative differential resistance (NDR) behavior of SymFETs leads to hysteresis in inverters and buffers, and can be used to build simple Schmitt-triggers. Further, pseudo-SymFET loads may be utilized in circuits similar to all-n-type or dynamic logic. For example, latches and flip-flops as well as NAND, NOR, IMPLY, and MAJORITY gates may employ SymFETs. Such SymFET-based devices require fewer transistors than static CMOS-based designs.

Devices for utilizing symFETs for low-power information processing

A random access memory architecture includes a first series connected pair of memory elements () having a first resistance and a second series connected pair of memory elements () having a second resistance coupled in parallel with the first series connected pair of memory elements, wherein a current flows in the first direction through both of the first and second series connected pair of memory elements. A sense amplifier () is coupled to an array () of MRAM cells (), each including a memory element, and includes a voltage bias portion (), the voltage bias portion including the first and second series connected pair of memory elements. The memory elements may be, for example, magnetic tunnel junctions.

Random access memory architecture including midpoint reference

A controller for a toggle memory that performs burst writes by reading a group of bits in the toggle memory and comparing each received data word of the burst with a portion of the group to determine which cells to toggle to enter the data of the burst write in the toggle memory. In one example the toggle memory includes magnetoresistive random access memory (MRAM) with cells using multiple free magnetic layers that toggle between states when subjected to a sequence of magnetic pulses along two directions. Because one read is performed for a group of data of the burst, the time needed to perform the burst write is reduced.

Toggle memory burst

An embedded memory system () uses an MRAM core () and error correction code (ECC) corrector circuitry (). The ECC corrector circuitry identifies soft memory bit errors which are errors primarily resulting from an MRAM bit not being correctly programmed. The errors are identified and corrected during a read or a write cycle and not necessarily when the memory is in a special test mode. As errors are corrected, the error corrections are counted by an error counter () to create a count value. The count value is stored in the MRAM core itself and can later be retrieved and read during a test mode for an indication of how many bit corrections are required for the MRAM core over a period of time. The count value is stored by using an unused portion of a write memory cycle during a read operation.

MRAM having error correction code circuitry and method therefor

A memory circuit includes a sense amplifier in which a single reference signal is compared to two data signals from two memory cells. The reference signal is generated from the combination of memory cells in opposite logic states. The data signal capacitance is matched to the reference signal capacitance. With reduced but matched capacitance both high speed and high sensitivity can be achieved.

Sense amplifier with multiple bits sharing a common reference

Each memory cell of an MRAM that uses toggle writing is written by applying to the memory cell a first field, then a combination of the first field and the second field, then the second field. The removal of the second field ultimately completes the writing of the memory cell. The combination of the first field and the second field is known to saturate a portion, the synthetic antiferromagnet (SAF), of the MRAM cell being written. This can result in not knowing which logic state is ultimately written. This is known to be worsened at higher temperatures. To avoid this deleterious saturation, the magnetic field is reduced during the time when both fields are applied. This is achieved by reducing the current that provides these fields from the current that is applied when only one of the fields is applied.

MRAM with a write driver and method therefor

A computer model simulation for an MRAM cell. In one example, the MRAM cell includes a magnetic tunnel junctions (MTJ) with multiple free magnetic layers. In one embodiment, the simulation implements a state machine whose states variables transition based on indications of magnetic fields passing thresholds. In one embodiment, the conductance values utilized from the model are derived from measured data that is curve fitted to obtain first and second order polynomial coefficient parameters to be used in the model.

Magnetoresistive random access memory simulation

A magnetoresistive random access memory (MRAM) () that is susceptible to a residual magnetic field is compensated during a write operation. A first magnetic field () is applied to a memory cell during a first time period, the first magnetic field having a first direction (y) and a first magnitude. A second magnetic field () is applied to the memory cell during a second time period and having a second direction (x) and a second magnitude. A third magnetic field () is applied to the memory cell during a third time period, wherein the third time period overlaps at least a portion of the second time period, the third magnetic field having a third direction (&#x2212;y) which is approximately opposite to the first direction of the first magnetic field. Currents are selectively applied through conductors in the memory cell to apply the three magnetic fields.

MRAM memory with residual write field reset

A magnetoresistive random access memory (MRAM) has separate read and write paths. This reduces the peripheral circuitry by not requiring switching between read and write functions on a particular line. By having the paths dedicated to either read signals or write signals, the voltage levels can be optimized for these functions. The select transistors, which are part of only the read function, may be of the low-voltage type because they do not have to receive the relatively higher voltages of the write circuitry. Similarly, the write voltages do not have to be degraded to accommodate the lower-voltage type transistors. The size of the overall memory is kept efficiently small while improving performance. The memory cells are grouped so that adjacent to groups are coupled to a common global bit line which reduces the space required for providing the capacitance-reducing group approach to memory cell selection.

MRAM architecture with electrically isolated read and write circuitry

A method and apparatus () for simulating a magnetoresistive random access memory (MRAM) () uses non-linear functions to model both non-linear magnetic tunnel junction (MTJ) effects and non-linear state switching effects. The method includes calculating a high threshold (T) and a low threshold (T) based on a function of the hard axis current (I). The easy axis current (I) is compared to the high threshold (T). If the easy axis current is greater than the high threshold, the MTJ resistance (R) is set to represent a stored high value. The easy axis current is compared to the low threshold. If the easy axis current is less than the low threshold, the MTJ resistance (R) is set to represent a stored low value. By using non-linear functions to model the MTJ effects and switching effects, the behavior of an MRAM () can be more accurately simulated.

Method and apparatus for simulating a magnetoresistive random access memory (MRAM)

A circuit and method of operation compensates for current pulses on a regulated voltage of a voltage supply. The regulated voltage supply is coupled to a plurality of loads that are enabled by a first set of control signals. The enable loads place current pulses having a predetermined plurality on the regulated voltage supply. A second set of control signals enable compensation circuitry to place current pulses of an opposite polarity on the regulated voltage supply. The loads are mimicked to generate a signal that approximates a current pulse length of the enabled loads. Another circuit generates a pulse that approximates a current pulse amplitude of the pulse caused by the enabled loads. By generating compensating pulses of opposite polarity having similar duration and amplitude as the pulses caused by the switching loads, the regulated voltage is more accurately maintained.

Circuit and method for current pulse compensation

In a magnetoresistive random access memory (MRAM), a magnetic tunnel junction (MTJ) () cell is stacked with an asymmetric tunnel device (). This device, when used in a crosspoint MRAM array, improves the sensing of the state or resistance of the MTJ cells. Each MTJ cell has at least two ferromagnetic layers () separated by an insulator (). The asymmetric tunnel device () is electrically connected in series with the MTJ cell and is formed by at least two conductive layers () separated by an insulator (). The asymmetric tunnel device may be a MIM (), MIMIM () or a MIIM (). Asymmetry results from conducting electrons in a forward biased direction at a significantly greater rate than in a reversed biased direction. Materials chosen for the asymmetric tunnel device are selected to obtain an appropriate electron tunneling barrier shape to obtain the desired rectifying current/voltage characteristic.

Magnetoresistive random access memory (MRAM) cell having a diode with asymmetrical characteristics

An MRAM is provided that minimizes the limits in MRAM density imposed by utilization of an isolation or select device in each memory cell. In addition, methods are provided for reading an MTJ in a ganged memory cell of the MRAM. The method includes determining an electrical value that is at least partially associated with a resistance of a ganged memory cell of the MRAM. The MTJ in the ganged memory cell is toggled and a second electrical value, which is at least partially associated with the resistance of the ganged memory cell, is determined after toggling the MTJ. Once the electrical value prior to the toggling and after the toggling is determined, the difference between the two electrical values is analyzed to determine the value of the MTJ.

Growing community of inventors

Austin, TX, United States of America

Joseph J Nahas