International Business Machines Corporation

Joseph Hromek

John M Lauffer

Kishor V Desai

Bernd Karl Appelt

Irving Memis

Robin A Susko

Andrew Michael Seman

Ronald A Kaschak

James Jens Hansen

Kailash C Joshi

David K Balkin

George C Phillips, Jr

Magan S Patel

Lawrence C Alexander

Octavio I Chirino

Temporary connections are formed to a flip-chip style chip having solder bumps or preforms protruding therefrom for testing and burn-in while avoiding distortion of the solder bumps or preforms and avoiding wear and damage to a test or burn-in jig such as a ball grid array by the use of a preferably resilient bucketed interposer which includes recesses which have a depth greater than the protrusion of the solder bumps or preforms and, preferably are narrowed at one side to a tear-drop shape. Metallization in the recesses and contacts on the interposer which mate with the test or burn-in jig are preferably textured with dendrites to be self-cleaning. A bevelled tongue and groove arrangement translates a slight compressive force to a slight shearing force between the interposer and the chip to ensure good connections to the protruding solder bumps or preforms on the chip. Any deformation of the solder bumps or preforms thus tends to only improve accuracy of positioning of the solder bumps or preforms and avoids solder voiding due to compression distortion of the solder bumps or preforms. Full burn-in and functional testing can then identify 'known good' chips or dies before package completion, particularly to avoid rework of modular circuit packages.

Apparatus and method for burn-in and testing of devices with solder

Circuit boards or cards containing metallic layers on opposite major surfaces of a dielectric substrate whereby electrical and/or thermal interconnection between the metallic layers is provided in vias that extend through one of the metallic layers, and the dielectric substrate and into the other metallic layer.

Electrical and/or thermal interconnections and methods for obtaining such

This is a microelectronic multilayer circuit structure having circuit compatibility encapsulated within the circuit package including conductive electrical interconnection means formed by uniquely metallizing the 'via' and/or blind interconnection holes within the circuit package. The assembly process provides means of uniformly metallizing the interlayer connecting holes.

Multilayer ceramic substrate structure

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Endwell, NY, United States of America

Joseph Hromek