International Business Machines Corporation

Globalfoundries Inc.

Other

Joseph Francis Shepard, Jr

Michael Patrick Chudzik

Louis L Hsu

Lawrence Alfred Clevenger

Carl John Radens

Rajarao Jammy

Min Dai

Jinping Liu

Rishikesh Krishnan

Shahab Siddiqui

Takashi Ando

Siddarth A Krishnan

Howard Hao Chen

Sampath Purushothaman

Martin Michael Frank

Robert H Dennard

Unoh Kwon

Evgeni Petrovich Gousev

Deborah A Neumayer

Chandrasekhar Narayan

Anna Wanda Topol

Barry P Linder

Bruce Kenneth Furman

Rama Divakaruni

Subhash Laxman Shinde

Yanfeng Wang

Claude Ortolland

David B Goland

Kenneth T Settlemyer, Jr

Maryjane Brodsky

David F Hilscher

Padraic C Shafer

Jean-Marc Rousseau

Jack Allan Mandelman

William R Tonti

Toshiharu Furukawa

Oleg Gluschenkov

Vijay Narayanan

Keith Kwong Hon Wong

Ryota Katsumata

Cyril Cabral, Jr

Christian Lavoie

Douglas Duane Coolbaugh

Eduard Albert Cartier

Sufi Zafar

Helmut Horst Tews

Bernhard Sell

Shesh Mani Pandey

Anthony I Chou

Jochen C Beintner

Paul Charles Jamison

Johnathan E Faltermeier

Ebenezer E Eshun

James Spiros Nakos

Keitaro Imai

Kwong Hon Wong

Fenton Read McFeely

Viraj Yashawant Sardesai

Matthias Goldbach

Alessandro Cesare Callegari

Yi Qi

Yiheng Xu

Zhenyu Hu

Kenneth Jay Stein

Harald Seidl

Oh-Jung Kwon

Christopher Peter D'Emic

Alessandro Curioni

Hsien-Ching Lo

Kunal Vaed

Zhiguo Sun

Michael Abramovich Gribelyuk

Huy Cao

Jay Sanford Burnham

Bharat V Krishnan

Paul Andrew Ronsheim

Uwe Schroeder

Irene Lennox McStay

Domingo A Ferrer

Moosung M Chae

Dianne L Lacey

Dirk Schumann

Kriteshwar Kaur Kohli

Rinus Tek Po Lee

Paul Daniel Kirsch

Sean M Polvino

Dong-Ick Lee

Kristen Scheer

Wanda Andreoni

Shahrukh Akbar Khan

Pei Zhao

Edward D Adams

Carlo A Pignedoli

Alina Vinslava

Joseph K Kassim

Keith K H Wong

Youngjin Choi

Sang Woo Lim

Heather Elizabeth Preuss

Kyung-Bum Koo

Methods of forming a field-effect transistor and structures for a field-effect transistor. A gate structure is formed that overlaps with a channel region beneath a top surface of a semiconductor fin. The semiconductor fin is etched with an anisotropic etching process to form a cavity having a sidewall with a planar section extending vertically toward the top surface of the semiconductor fin and adjacent to the channel region in the semiconductor fin. The semiconductor fin is then etched with an isotropic etching process that widens the cavity at the top surface while preserving verticality of the planar section.

Single-curvature cavity for semiconductor epitaxy

An insulator is formed by flowable chemical vapor deposition (FCVD) process. The insulator is cured by exposing the insulator to ultraviolet light while flowing ozone over the insulator to produce a cured insulator. The curing process forms nitrogen, hydrogen, nitrogen monohydride, or hydroxyl-rich atomic clusters in the insulator. Following the curing process, these methods select wavelengths of microwave radiation (that will be subsequently used during annealing) so that such wavelengths excite the nitrogen, hydrogen, nitrogen monohydride, or hydroxyl-rich atomic clusters. Then, these methods anneal the cured insulator by exposing the cured insulator to microwave radiation in an inert (e.g., non-oxidizing) ambient atmosphere, at a temperature below 500&#xb0; C., so as to increase the density of the cured insulator.

Microwave annealing of flowable oxides with trap layers

A method for forming a precision resistor or an e-fuse structure where tungsten silicon is used. The tungsten silicon layer is modified by implanting nitrogen into the structure.

Modified tungsten silicon

The present disclosure relates to semiconductor structures and, more particularly, to airgaps which isolate metal lines and methods of manufacture. The structure includes: a plurality of metal lines formed on an insulator layer; and a dielectric material completely filling a space having a first dimension between metal lines of the plurality of metal lines and providing a uniform airgap with a space having a second dimension between metal lines of the plurality of metal lines. The first dimension is larger than the second dimension.

Airgaps to isolate metallization features

A surface of a semiconductor-containing dielectric material/oxynitride/nitride is treated with a basic solution in order to provide hydroxyl group termination of the surface. A dielectric metal oxide is subsequently deposited by atomic layer deposition. The hydroxyl group termination provides a uniform surface condition that facilitates nucleation and deposition of the dielectric metal oxide, and reduces interfacial defects between the oxide and the dielectric metal oxide. Further, treatment with the basic solution removes more oxide from a surface of a silicon germanium alloy with a greater atomic concentration of germanium, thereby reducing a differential in the total thickness of the combination of the oxide and the dielectric metal oxide across surfaces with different germanium concentrations.

Hydroxyl group termination for nucleation of a dielectric metallic oxide

One aspect of the disclosure relates to and integrated circuit structure and methods of forming the same. The integrated circuit structure may include: a thin gate dielectric device on a substrate, the thin gate dielectric device including: a first interfacial layer over a set of fins within the substrate, wherein the interfacial layer has a thickness of approximately 1.0 nanometers (nm) to approximately 1.2 nm; and a thick gate dielectric device on the substrate adjacent to the thin gate dielectric device, the thick gate dielectric device including: a second interfacial layer over the set of fins within the substrate; and a nitrided oxide layer over the second interfacial layer, wherein the nitrided oxide layer includes a thickness of approximately 3.5 nm to approximately 5.0 nm.

Integrated circuit structure having thin gate dielectric device and thick gate dielectric device

A semiconductor device is disclosed. The semiconductor device includes a substrate; and a gate structure disposed directly on the substrate, the gate structure including: a graded region with a varied material concentration profile; and a metal layer disposed on the graded region.

Semiconductor device including graded gate stack, related method and design structure

A method of forming a semiconductor device is disclosed. The method includes: forming a dielectric region on a substrate; annealing the dielectric region in an environment including ammonia (NH); monitoring a nitrogen peak of at least one of the substrate and the dielectric region during the annealing; and adjusting a parameter of the environment based on the monitoring of the nitrogen peak.

Method of manufacturing scaled equivalent oxide thickness gate stacks in semiconductor devices and related design structure

Embodiments include methods of forming an nFET-tuned gate dielectric and a pFET-tuned gate dielectric. Methods may include forming a high-k layer above a substrate having a pFET region and an nFET region, forming a first sacrificial layer, a pFET work-function metal layer, and a second sacrificial layer above the first high-k layer in the pFET region, and an nFET work-function metal layer above the first high-k layer in the nFET region and above the second sacrificial layer in the pFET region. The first high-k layer then may be annealed to form an nFET gate dielectric layer in the nFET region and a pFET gate dielectric layer in the pFET region. The first high-k layer may be annealed in the presence of a nitrogen source to cause atoms from the nitrogen source to diffuse into the first high-k layer in the nFET region.

Concurrently forming nFET and pFET gate dielectric layers

A composite high dielectric constant (high-k) gate dielectric includes a stack of a doped high-k gate dielectric and an undoped high-k gate dielectric. The doped high-k gate dielectric can be formed by providing a stack of a first high-k dielectric material layer and a dopant metal layer and annealing the stack to induce the diffusion of the dopant metal into the first high-k dielectric material layer. The undoped high-k gate dielectric is formed by subsequently depositing a second high-k dielectric material layer. The composite high-k gate dielectric can provide an increased gate-leakage oxide thickness without increasing inversion oxide thickness.

Composite high-k gate dielectric stack for reducing gate leakage

A method of creating insulating layers on different semiconductor materials includes providing a substrate having disposed thereon a first material and a second material, the second material having a chemical composition different from the first material; non-epitaxially depositing a continuous sacrificial layer of approximately constant thickness onto the first material and the second material, and then converting the sacrificial layer into a layer consisting essentially of SiOwithout oxidizing more than 10 angstroms into the second material. A structure includes a silicon nitride film disposed conformally on a silicon layer and a silicon germanium layer; a SiOlayer is disposed on the silicon nitride film.

Insulating layers on different semiconductor materials

A method of fabricating a silicon-containing oxide layer that includes providing a chemical oxide layer on a surface of a semiconductor substrate, removing the chemical oxide layer in an oxygen-free environment at a temperature of 1000&#xb0; C. or greater to provide a bare surface of the semiconductor substrate, and introducing an oxygen-containing gas at a flow rate to the bare surface of the semiconductor substrate for a first time period at the temperature of 1000&#xb0; C. The temperature is then reduced to room temperature during a second time period while maintaining the flow rate of the oxygen containing gas to provide a silicon-containing oxide layer having a thickness ranging from 0.5 &#x212b; to 10 &#x212b;.

Fabrication of silicon oxide and oxynitride having sub-nanometer thickness

A method includes providing an SOI substrate including a layer of silicon disposed atop a layer of an oxide, the layer of an oxide being disposed atop the semiconductor substrate; forming a deep trench having a sidewall extending through the layer of silicon and the layer of an oxide and into the substrate; depositing a continuous spacer on the sidewall to cover the layer of silicon, the layer of an oxide and a part of the substrate; depositing a first conformal layer of a conductive material throughout the inside of the deep trench; creating a silicide within the deep trench in regions extending through the sidewall into an uncovered part of the substrate; removing the first conformal layer from the continuous spacer; removing the continuous spacer; depositing a layer of a high k dielectric material throughout the inside of the deep trench, and depositing a second conformal layer of a conductive material onto the layer of a high-k dielectric material.

Method of fabricating a deep trench (DT) metal-insulator-metal (MIM) capacitor

The present invention provides a gate stack structure that has high mobilities and low interfacial charges as well as semiconductor devices, i.e., metal oxide semiconductor field effect transistors (MOSFETs) that include the same. In the semiconductor devices, the gate stack structure of the present invention is located between the substrate and an overlaying gate conductor. The present invention also provides a method of fabricating the inventive gate stack structure in which a high temperature annealing process (on the order of about 800&#xb0; C.) is employed. The high temperature anneal used in the present invention provides a gate stack structure that has an interface state density, as measured by charge pumping, of about 8&#xd7;10charges/cmor less, a peak mobility of about 250 cmV-s or greater and substantially no mobility degradation at about 6.0&#xd7;10inversion charges/cmor greater.

Method of forming metal/high-&#x3ba; gate stacks with high mobility

Growing community of inventors

Poughkeepsie, NY, United States of America

Joseph Francis Shepard, Jr