National Semiconductor Corporation

Integrated Silicon Solution Incorporated

Joseph E Herbst

Ian Edward Davis

Jamie J LeVasseur

A two port high speed integrated circuit memory device that includes a bus transceiver, a memory array and a decoder. The present invention provides a processor high speed access to the internal memory array via very low capacitive load address and data buses. The present invention also buffers a secondary bus to provide access to slower-speed local devices. The bus transceiver transfers address, data and control signals between the primary and secondary port and also couples signals to the internal memory array. The bus transceiver includes an input data bus, an output data bus, and an address and control bus. Each of these separate buses include a buffer at the primary and secondary port to minimize capacitive loading. The decoder in the two port memory device decodes memory chip select signals and control signals that define the operational mode of the device. To save power the present invention provides an operational mode in which primary bus signals are not reflected to the secondary bus unless the internal memory array is not selected by the chip selects. In an enhanced mode the two port memory device includes a ready signal generator feature, and chip select lines are converted into additional address input lines.

Integrated circuit memory with a bus transceiver

A Cache Memory Controller which operates in conjunction with a TAG Random Access Memory (TAG RAM) coupled to the lower order bits on a host address bus is provided. The Cache Memory Controller selects the data to be written to TAG RAM from two or more sources. One of these sources provides snoop address signals and another provides invalidating signals. During a read operation, the lower order bits of the address on the address bus address the TAG RAM while the n higher order bits are passed to a shifter and to a compare circuit. In response to the lower order bits of the address provided, the TAG RAM generates an n-bit TAG data output signal. If this data output compares exactly with the n higher order bits on the host address bus, the compare circuit will indicate a hit. If the compare circuit does not indicate a hit, the n higher order address bits are written into the TAG RAM. Data from main memory is then loaded into the cache memory. During a write operation, the lower order bits address the TAG RAM, with the n higher order being passed to the shifter as before. Upon the occurrence of a TAG write enable signal, the output of the shifter is written into the TAG RAM as data at the TAG RAM address corresponding to the address on the lower order address lines of the host bus. Data is then loaded from main memory into the cache memory.

Method and apparatus for providing a readable and writable cache tag

A method and apparatus are provided for controlling clocks for a processor and L2 cache. The clock signal to an L2 cache may be shut down in order to conserve power. Due to the nature of CMOS circuitry typically comprising the SRAM in an L2 cache, shutting down the clock signal to the L2 cache may significantly reduce the amount of power consumed by the L2 cache. A clock control circuitry may be provided to generate and control clock signals to a processor (e.g., Pentium.RTM. processor) and an L2 cache. Controllable clock skew adjustment may be provided to adjust relative timing between clock signals. Skew adjustment for the L2 cache clock may be provided with an AND gate for interrupting the clock signal. The AND gate may be controlled by one of a number of signals indicating status of the L2 cache. Address strobe, L2 idle, or pipelining conditions may determine whether the clock signal to the L2 cache may be interrupted. The use of combinational logic circuitry allows for seamless shutdown and restarting of the L2 cache clock signal. The present invention has particular application to a system where interface circuits may be used to interface a Pentium.RTM. processor to a VL bus.

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Milpitas, CA, United States of America

Joseph E Herbst