Texas Instruments Corporation

Triquint Semiconductors Texas, Inc.

Joseph B Delaney

Clyde R Fuller

Thomas E Nagle

Robbie W Skinner

Kirk Edwin Bracey

Timothy S Henderson

Betty S Mercer

Generally, and in one form of the invention, a method is disclosed for forming an ohmic contact on a GaAs surface,comprising the steps of depositing a layer of InGaAs,over the GaAs surface,, and depositing a layer of TiW,on the layer of InGaAs,, whereby a reliable and stable electrical contact is established to the GaAs surface,and whereby Ti does not generally react with the In.

Method of forming a low-resistance contact on compound semiconductor

Generally, and in one form of the invention, a method is disclosed for forming an ohmic contact on a GaAs surface 20 comprising the steps of depositing a layer of InGaAs 22 over the GaAs surface 20, and depositing a layer of TiW 24 on the layer of InGaAs 22, whereby a reliable and stable electrical contact is established to the GaAs surface 20 and whereby Ti does not generally react with the In.

Low-resistance contact on a compound semiconductor

A process and structure for an improved collector-up bipolar transistor. The base is formed after the emitter is implanted to eliminate base damage during oxygen implantation typical in prior art collector-up bipolar transistors. In a preferred embodiment, an emitter layer of GaAlAs is implanted with oxygen in the extrinsic emitter region to damage the material and make it insulative. The base is epitaxially grown at low temperature to insure the emitter material remains damaged and insulative.

Collector up heterojunction bipolar transistor

Method for forming collector up heterojunction bipolar transistor having

The disclosure relates to a semiconductor circuit on a single chip, preferably of gallium arsenide, wherein insulating layers with vias therein for receiving metallization include a thin silicon nitride layer beneath a relatively much thicker silicon oxide layer with the nitride exposed on the via side walls to contact gold in the metallization within the via. The disclosure further includes metallization formed as a TiW/Au/TiW sandwich wherein the TiW layer contacting the insulator on the substrate is formed of a first tensile film of TiW with a compressive film of TiW of substantially the same thickness thereover and in contact therewith to lower the tensile force applied by the tensile layer, yet maintain the resultant force tensile.

Semiconductor circuit

Generally, and in one form of the invention a method for making a heterojunction bipolar transistor comprising the steps of forming a compound semiconductor material structure comprised of a plurality of layers, wherein at least one of the plurality of layers is comprised of a first material (e.g. GaAs 36) and at least one of the remaining of the plurality of layers is comprised of a second material (e.g. AlGaAs 32); and etching the layers comprised of the first material with an etchant that does not appreciably etch the layers of the second material is disclosed. A surprising aspect of this invention is that no additional etch stop layer was added in the material structure. Etchants were found that stop on the wide band gap emitter layer (e.g. AlGaAs) usually found in heterojunction bipolar transistors despite the similarity of the materials. An advantage of this method is that a reference point for timing subsequent etches is established at a point other than the top of the uppermost of the layers, thereby improving the accuracy with which the depth of the subsequent etching can be controlled. Improved etch depth accuracy directly relates to more producible and higher yield heterojunction bipolar transistor devices. Other devices, systems, and methods are also disclosed.

Growing community of inventors

Plano, TX, United States of America

Joseph B Delaney