Infineon Technologies Ag

Infineon Technologies Austria Ag

Qimonda Ag

Infineon Technoloiges Austria Ag

Tinfineon Technologies Austria Ag

Josef Hoeglauer

Ralf Otremba

Xaver Schloegel

Klaus Schiess

Juergen Schredl

Joachim Mahler

Petteri Palm

Frank Daeche

Chooi Mei Chong

Gerhard Noebauer

Markus Dinkel

Erwin Huber

Thorsten Meyer

Khalil Hosseini

Helmut Strack

Angela Kessler

Maciej Wojnowski

Andrew Neil Sawle

Teck Sim Lee

Stefan Landau

Henrik Ewe

Zeeshan Umar

Eung San Cho

Matthias Stecher

Anton Prueckl

Guenther Lohmann

Horst Theuss

Edward Fuergut

Manfred Mengel

Martin Gruber

Thorsten Scharf

Adolf Koller

Kok Yau Chua

Reinhard Ploss

Uwe Kirchner

Johannes Lodermeyer

Josef Maerz

Michael Juerss

Fabian Schnoy

Soon Hock Tong

Riccardo Pittassi

Bernd Roemer

Ulrich Froehler

Kwai Hong Wong

Bun Kian Tay

Tino Karczeweski

Martin Standing

Georg Meyer-Berg

Chuan Cheah

Markus Brunnbauer

Jochen Dangelmaier

Chau Fatt Chiang

Matteo-Alessandro Kutschak

Swee Kah Lee

Matthias Strassburg

Reimund Engl

Wolfram Hable

Thomas Behrens

Robert Fehler

Lee Shuang Wang

Werner Kroeninger

Chee Voon Tan

Sergey Yuferev

Ottmar Geitner

Frank Kahlmann

Khay Chwan Saw

Tobias Polster

Abdul Rahman Mohamed

Josef Schwaiger

Amirul Afiq Hud

Paul Armand Asentista Calo

Wolfgang Peinhopf

Fong Lim

Ludwig Schneider

Mei Qi Tay

Ida Fischbach

Roveendra Paul

Mei Yih Goh

Hao Zhuang

Chiah Chin Lim

A semiconductor device is disclosed. In one example, the semiconductor device includes a semiconductor chip including a first chip contact pad on a first chip main surface. The semiconductor device further includes a first electrically conductive layer arranged over the first chip main surface and electrically coupled to the first chip contact pad, wherein the first electrically conductive layer extends in a direction parallel to the first chip main surface. An electrical through connection is electrically coupled to the first electrically conductive layer and to a second electrically conductive layer, wherein the electrical through connection extends in a direction perpendicular to the first chip main surface, and wherein, in a top view of the first chip main surface, the electrical through connection and the semiconductor chip are non-overlapping.

Semiconductor devices including parallel electrically conductive layers

In an embodiment, a leadframe includes a first electrically conductive part and a second electrically conductive part, each having an outer surface arranged to provide substantially coplanar outer contact areas having a footprint and an inner surface opposing the outer surface, the first part being spaced apart from the second part by a gap, a first recess arranged in the inner surface of the first part, a second recess arranged in the inner surface of the second part, and a first electrically conductive insert that is arranged in, and extends between, the first recess and the second recess and bridges the gap between the first part and the second part.

Leadframe, semiconductor package and method

A method of processing a semiconductor wafer includes: forming an electronic device at each die location of the semiconductor wafer; partially forming a frontside metallization over a frontside of the semiconductor wafer at each die location; partially forming a backside metallization over a backside of the semiconductor wafer at each die location; and after partially forming both the frontside metallization and the backside metallization but without completing either the frontside metallization or the backside metallization, singulating the semiconductor wafer between the die locations to form a plurality of individual semiconductor dies, wherein the partially formed frontside metallization and the partially formed backside metallization have a same composition. Semiconductor dies and methods of producing semiconductor modules are also described.

Method of processing a semiconductor wafer, semiconductor die, and method of producing a semiconductor module

A method of forming a semiconductor module comprises forming a laminate structure having an electrically insulating core layer with opposing first and second sides, a first redistribution layer arranged on the first side and a second redistribution layer arranged on the second side. First and second transistor devices are coupled to form a half-bridge circuit. Bots transistor devices have a first side at which a cell field is arranged and an opposing second side. A control chip has a first side with contact pads. The transistor devices and control chip are arranged laterally adjacent one another and embedded in the core layer. The first side of the control chip and one transistor device and the second side of the other transistor device face towards the first redistribution layer on the first side of the core layer.

Method of forming a semiconductor module

A package and method of manufacturing is disclosed. In one example, the package which comprises a carrier with at least one component mounted on the carrier. A clip is arranged above the carrier and having a through hole. At least part of at least one of the at least one component and/or at least part of an electrically conductive connection element electrically connecting the at least one component is at least partially positioned inside the through hole.

Package with clip having through hole accommodating component-related structure

A power semiconductor system includes: a power stage module having one or more power transistor dies attached to or embedded in a first printed circuit board; and an inductor module attached to the power stage module and having an inductor electrically connected to an output node of the power stage module. The inductor includes windings patterned into a second printed circuit board of the inductor module.

Power semiconductor system having an inductor module attached to a power stage module

A semiconductor package includes a semiconductor die having opposing first and second main surfaces, a first power electrode on the first main surface and a second power electrode on the second main surface, a first lead having an inner surface attached to the first power electrode and a distal end having a first protruding side face extending substantially perpendicularly to the first main surface of the die, a second lead having an inner surface attached to the second power electrode and a distal end having a second protruding side face extending substantially perpendicularly to the second main surface of the die, and a mold compound enclosing at least part of the die and at least part of the first and second leads. The first lead includes a recess positioned in an edge of the inner surface. The second lead includes a recess positioned in an edge of the inner surface.

Semiconductor package, semiconductor module and methods for manufacturing a semiconductor package and a semiconductor module

A semiconductor module includes a laminate structure having an electrically insulating core layer with opposing first and second sides, a first redistribution layer arranged on the first side and a second redistribution layer arranged on the second side. First and second transistor devices are coupled to form a half-bridge circuit. Both transistor devices have a first side at which a cell field is arranged and an opposing second side. A control chip has a first side with contact pads. The transistor devices and control chip are arranged laterally adjacent one another and embedded in the core layer. The first side of the control chip and one transistor device and the second side of the other transistor device face towards the first redistribution layer on the first side of the core layer.

Semiconductor module

A method includes: arranging a semiconductor device on a redistribution substrate, the device having a first power electrode and a control electrode on a first surface and a second power electrode on a second surface, the redistribution substrate having an insulating board having a first major surface and a second major surface having solderable contact pads, so that the first power electrode is arranged on a first conductive pad and the control electrode is arranged on a second conductive pad on the first major surface; arranging a contact clip such that a web portion is arranged on the second power electrode and a peripheral rim portion is arranged on a third conductive pad on the first major surface; and electrically coupling the first power electrode, control electrode and peripheral rim portion to the respective conductive pads and electrically coupling the web portion to the second power electrode.

Method of fabricating a semiconductor package

A method of manufacturing a power semiconductor system includes providing a power module having one or more power transistor dies and attaching an inductor module to the power module such that the inductor module is electrically connected to a node of the power module. The inductor module includes a substrate with a magnetic material and windings at one or more sides of the substrate. Further methods of manufacturing power semiconductor systems and methods of manufacturing inductor modules are also described.

Method of manufacturing a power semiconductor system

A molded semiconductor package includes a lead frame having one or more first leads monolithically formed with a die pad and extending outward from the pad in a first direction. A semiconductor die is attached to the die pad at a first side of the die. A metal clip of a clip frame is attached to a power terminal at a second side of the die. One or more second leads monolithically formed with the metal clip extend outward from the clip in a second direction different than the first direction. A mold compound embeds the die. The first lead(s) and the second lead(s) are exposed at different sides of the mold compound and do not vertically overlap with one another. Within the mold compound, the clip transitions from a first level above the power terminal to a second level in a same plane as the leads.

Clip frame assembly, semiconductor package having a lead frame and a clip frame, and method of manufacture

In an embodiment, a semiconductor package includes a package footprint having a plurality of solderable contact pads, a semiconductor device having a first power electrode and a control electrode on a first surface and a second power electrode on a second surface, a redistribution substrate having an insulating board, wherein the first power electrode and the control electrode are mounted on a first major surface of the insulating board and the solderable contact pads of the package footprint are arranged on a second major surface of the insulating board, and a contact clip having a web portion and one or more peripheral rim portions. The web portion is mounted on and electrically coupled to the second power electrode and the peripheral rim portion is mounted on the first major surface of the insulating board.

Semiconductor package and method of fabricating a semiconductor package

A package encloses a power semiconductor die and has a package body with a top side, footprint side and sidewalls. The die has first and second load terminals and blocks a blocking voltage between the load terminals. The package further includes: a lead frame structure for electrically and mechanically coupling the package to a support, the lead frame structure including an outside terminal extending out of the package footprint side and/or out of one of the package sidewalls and electrically connected with the first load terminal; and a top layer arranged at the package top side and electrically connected with the second load terminal. A heat spreader is mounted onto the top layer with a bottom surface facing the top layer. The area of the top surface of the heat spreader is greater than the area of the bottom surface.

Method of producing an SMD package with top side cooling

A method of manufacturing a power semiconductor system includes providing a power stage module having one or more power transistor dies attached to or embedded in a first printed circuit board and attaching an inductor module to the power stage module such that the inductor module is electrically connected to an output node of the power stage module. The inductor module includes a ferrite sheet embedded in a second printed circuit board and windings patterned into the second printed circuit board. Further methods of manufacturing power semiconductor systems and methods of manufacturing inductor modules are also described.

Methods of manufacturing inductor modules and power semiconductor systems having inductor modules

Growing community of inventors

Heimstetten, Germany

Josef Hoeglauer