International Business Machines Corporation

Jose Angel Paredes

Peter Juergen Klim

Sam Gat-Shang Chu

Michael Ju Hyeok Lee

Dung Q Nguyen

Brian William Thompto

George McNeil Lattimore

David R Terry

Dhivya Jeganathan

Hung Qui Le

Scott Barnett Swaney

Michael James Mack

Andrew James Bianchi

David Allen Hrusecky

Susan Elizabeth Eisen

Robert Allen Cordes

Michael J Lee

Saiful Islam

Sam G Chu

Jennifer L Molnar

Shelton Siuwah Leung

James Allan Kahle

Gus Wai-Yan Yeung

Timothy Michael Skergan

Donald George Mikan, Jr

Bruce Joseph Ronchetti

Larry Edward Thatcher

James Wilson Bishop

Eric Jason Fluhr

Philip George Shephard, Iii

Terry Lee Leasure

Jafar Nahidi

Joaquin Hinojosa

Neil R Vanderschaaf

Ed Seewann

Binta Minesh Patel

Embodiments described herein include a computing system that permits partial writes into a memory element&#x2014;e.g., a register on a processor. For example, the data to be written into the memory element may be spread across multiple sources. The register may receive data from two different sources at different times and perform two separate partial write commands to store the data. Embodiments herein generate an ECC value for each of the partial writes. That is, when storing the data of the first partial write, the computing system generates a first ECC value for the data in the first partial write and stores this value in the memory element. Later, when performing the second partial write, the computing system generates a second ECC value for this data which is also stored in the memory element.

Partial ECC mechanism for a byte-write capable register

Generating ECC values for byte-write capable registers

Operation of a multi-slice processor that includes a plurality of execution slices and a load/store superslice, where the load/store superslice includes a set predict array, a first load/store slice, and a second load/store slice. Operation of such a multi-slice processor includes: receiving a two-target load instruction directed to the first load/store slice and a store instruction directed to the second load/store slice; determining a first subset of ports of the set predict array as inputs for an effective address for the two-target load instruction; determining a second subset of ports of the set predict array as inputs for an effective address for the store instruction; and generating, in dependence upon logic corresponding to the set predict array that is less than logic implementing an entire load/store slice, output for performing the two-target load instruction in parallel with generating output for performing the store instruction.

Operation of a multi-slice processor implementing simultaneous two-target loads and stores

Partial ECC handling for a byte-write capable register

Recovery circuits react to errors in a processor core by waiting for an error-free completion of any pending store-conditional instruction or a cache-inhibited load before ceasing to checkpoint or backup progress of a processor core. Recovery circuits remove the processor core from the logical configuration of the symmetric multiprocessor system, potentially reducing propagation of errors to other parts of the system. The processor core is reset and the checkpointed values may be restored to registers of the processor core. The core processor is allowed not just to resume execution just prior to the instructions that failed to execute correctly the first time, but is allowed to operate in a reduced execution mode for a preprogrammed number of groups. If the preprogrammed number of instruction groups execute without error, the processor core is allowed to resume normal execution.

Processor instruction retry recovery

A logic gate is described that implements complex logic within a memory array. The logic gate receives at least three of a first storage cell signal, a second storage cell signal, a first external signal, or a second external signal at a first input circuitry and second input circuitry. The logic gate then performs one of a set of logic functions using the first storage cell signal, the second storage cell signal, the first external signal, or the second external signal. The set of logic functions includes at least one of a matching function, an OR-AND function, or an AND function.

Method and apparatus for implementing complex logic within a memory array

A register file is often used within integrated circuitry to temporarily hold data. Sometimes this data needs to be retained within the register file for a period of time, such as when there is a stall operation. Conventional register files have utilized a hold multiplexor to perform such a stall operation. The multiplexor however inserts a delay that is undesirable in high performance integrated circuitry. The multiplexor is replaced with a tri-state inverter coupled to the global bit line of the register file, which minimizes this additional delay from the register file data access time.

Register file

A system and method of selective row energization based on write data, with a selective row energization system including a storage arrayhaving M rowsand N columns; an N-bit data word register; a uniform-detect circuitresponsive to a data word to generate a uniform word data bit having a first value when the data word is uniform; an M-bit uniform-detect registerhaving M uniform-detect latches, each being associated with one of the M rowsand storing the uniform word data bit for the data word stored in the associated M row; and an M-bit row driver deviceresponsive to the uniform word data bit for each of the M rowsto inhibit energization of the M rowsfor which the uniform word data bit is the first value.

System and method of selective row energization based on write data

A method, system and apparatus for detecting soft errors in non-dataflow circuits. In a preferred embodiment, input is received at a latch system. The latch system consists of two pairs of latches. The second pair of latches is parallel to the first pair of latches. Both pairs of latches capture the input. However, the second pair of latches captures the input later in time relative to the first pair of latches latch. The captured input is then transferred from the first latch in each pair of latches to the second latch in each pair of latches. A comparison is made of the input in the two second latches. If the input captured in the two second latches is not the same, then a message is sent to a recovery unit.

Transient noise detection scheme and apparatus

A method and apparatus are provided for dispatch group checkpointing in a microprocessor, including provisions for handling partially completed dispatch groups and instructions which modify system coherent state prior to completion. An instruction checkpoint retry mechanism is implemented to recover from soft errors in logic. The processor is able to dispatch fixed point unit (FXU), load/store unit (LSU), and floating point unit (FPU) or vector multimedia extension (VMX) instructions on the same cycle. Store data is written to a store queue when a store instruction finishes executing. The data is held in the store queue until the store instruction is checkpointed, at which point it can be released to the coherently shared level 2 (L2) cache.

Method for checkpointing instruction groups with out-of-order floating point instructions in a multi-threaded processor

Method for implementing complex logic within a memory array

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Austin, TX, United States of America

Jose Angel Paredes