Commissariat &#xc0; L'&#xc9;nergie Atomique Et Aux &#xc9;nergies Alternatives

Joris Lacord

Sylvain Barraud

Thierry Poiroux

Olivier Rozeau

Marie-Anne Jaud

Sébastien Martinie

François Tcheme Wakam

A microelectronic device includes a field-effect n-MOS transistor, a first N-doped zone, constituting one from among the drain and the source of the n-MOS transistor and a second N-doped zone, constituting the other from among the drain and the source of the n-MOS transistor. The device further includes a field-effect p-MOS transistor, a first P-doped zone, constituting one from among the drain and the source of the p-MOS transistor, a dielectric layer in contact with the doped zones and a rear gate. The n-MOS transistor and the p-MOS transistor are separated by a PN junction.

Microelectronic device with two field-effect transistors

A method for producing an FET transistor includes producing a transistor channel, comprising at least one semiconductor nanowire arranged on a substrate and comprising first and second opposite side faces; producing at least two dummy gates, each arranged against one of the first and second side faces of the channel; etching a first of the two dummy gates, forming a first gate location against the first side face of the channel; producing a first gate in the first gate location and against the first side face of the channel; etching a second of the two dummy gates, forming a second gate location against the second side face of the channel; and producing a second gate in the second gate location and against the second side face of the channel.

Method of fabricating a field effect transistor

Embodiments of the invention determine intrinsic parameters of stacked nanowires/nanosheets GAA MOSFETs comprising Nnanowires and/or nanosheets, each nanowire/nanosheet being surrounded in an oxide layer, the oxide layers being embedded in a common gate, wherein the method comprises the following steps:

Computer implemented method for determining intrinsic parameter in a stacked nanowires MOSFET

A method for programming a one-transistor dynamic memory cell of A2RAM type. The A2RAM memory cell includes a source and a drain doped of a first conductivity type, a body region arranged between the source and the drain, and an insulated gate arranged facing the body region. The body region includes first and second portions extending parallel to the insulated gate, the first portion being doped of a second conductivity type opposite to the first conductivity type and arranged between the insulated gate and the second portion, doped of the first conductivity type. The programming method includes biasing the transistor in an off state by electrical potentials applied to the drain and the gate. The drain potential and the gate potential are chosen in such a way as to create charge carriers by impact ionisation in the second portion.

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Grenoble, France

Joris Lacord