Texas Instruments Corporation

Imec

Interuniversitair Microelektronica Centrum (Imec)

Taiwan Semiconductor Manufacturing Comp. Ltd.

Koninklijke Philips Corporation N.v.

National University of Singapore

Katholieke Universiteit Leuven, Ku Leuven R&d

Panasonic Corporation

Nxp B.v.

Jorge Adrian Kittl

Johan Swerts

Sven Van Elshocht

Anne Lauwers

Amitabh Jain

Qi-Zhong Hong

Anabela Veloso

Peijun Chen

Mihaela Ioana Popovici

HongYu Yu

Mark R Visokay

Marcus Johannes Henricus Van Dal

Shou-Zen Chang

Dim-Lee Kwong

Roger Loo

Stefan Jakschik

Koen Martens

Min-Soo Kim

Christoph Adelmann

Vincent Maurice McNeil

Serge Biesemans

Kazuyuki Tomida

Malgorzata Pawlak

Chen JingDe

Li Mingfu

Anil Kottantharyil

Hong Yu Yu

Anil Kottantharayil

The disclosure provides a method for producing a stack of layers on a semiconductor substrate. The method includes producing a substrate a first conductive layer; and producing by ALD a sub-stack of layers on said conductive layer, at least one of said layers of the sub-stack being a TiOlayer, the other layers of the sub-stack being layers of a dielectric material having a composition suitable to form a cubic perovskite phase upon crystallization of said sub-stack of layers. Crystallization is obtained via heat treatment. When used in a metal-insulator-metal capacitor, the stack of layers can provide improved characteristics as a consequence of the TiOlayer being present in the sub-stack.

Metal-insulator-metal capacitor and method for manufacturing thereof

Disclosed are methods for manufacturing semiconductor devices and the devices thus obtained. In one embodiment, the method comprises obtaining a semiconductor substrate comprising a germanium region doped with n-type dopants at a first doping level and forming an interfacial silicon layer overlying the germanium region, where the interfacial silicon layer is doped with n-type dopants at a second doping level and has a thickness higher than a critical thickness of silicon on germanium, such that the interfacial layer is at least partially relaxed. The method further includes forming over the interfacial silicon layer a layer of material having an electrical resistivity smaller than 1&#xd7;10&#x3a9;cm, thereby forming an electrical contact between the germanium region and the layer of material, wherein the electrical contact has a specific contact resistivity below 10&#x3a9;cm.

Method of manufacturing low resistivity contacts on n-type germanium

Methods of manufacturing metal-insulator-metal capacitor structures, and the metal-insulator-metal capacitor structures obtained, are disclosed. In one embodiment, a method includes providing a substrate, forming on the substrate a first metal layer comprising a first metal, and using atomic layer deposition with an HO oxidant to deposit on the first metal layer a protective layer comprising TiO. The method further includes using atomic layer deposition with an Ooxidant to deposit on the protective layer a dielectric layer of a dielectric material, and forming on the dielectric layer a second metal layer comprising a second metal. In another embodiment, a metal-insulator-metal capacitor includes a bottom electrode comprising a first metal, a protective layer deposited on the bottom electrode and comprising TiO, a dielectric layer deposited on the protective layer and comprising a dielectric material, and a top electrode formed on the dielectric layer and comprising a second metal.

Method for producing a metal-insulator-metal capacitor for use in semiconductor devices

The present disclosure is related to a dielectric layer comprising a rare-earth aluminate (REAlOwith 0&#x3c;x&#x3c;2) and having a perovskite crystalline structure, wherein the rare-earth aluminate comprises a rare-earth element having an atomic number higher than or equal to 63 and lower than or equal to 71. The disclosure also relates to method of manufacturing of a dielectric stack and a dielectric stack comprising said rare-earth aluminate dielectric layer and further comprising a template stack comprising at least an upper template layer, wherein the upper template layer has a perovskite structure, and wherein the upper template layer is underlying and in contact with the rare-earth aluminate dielectric layer. In a preferred embodiment the dielectric stack further comprises a lower template layer having a crystalline structure, wherein the lower template layer is underlying and in contact with the upper template layer.

Dielectric layer for flash memory device and method for manufacturing thereof

According to one embodiment of the invention, a method for nickel silicidation includes providing a substrate having a source region, a gate region, and a drain region, forming a source in the source region and a drain in the drain region, annealing the source and the drain, implanting, after the annealing the source and the drain, a heavy ion in the source region and the drain region, depositing a nickel layer in each of the source and drain regions, and heating the substrate to form a nickel silicide region in each of the source and drain regions by heating the substrate.

Method and system for improved nickel silicide

NiSiFUSI gates can be formed inter alia by further reaction of NiSi/NiSi gate stacks. NiSibehaves similarly to NiSi in terms of work function values, and of modulation with dopants on SiO, in contrast to Ni-rich silicides which have significantly higher work function values on HfSiOand negligible work function shifts with dopants on SiO. Formation of NiSican applied for applications targeting NiSi FUSI gates, thereby expanding the process window without changing the electrical properties of the FUSI gate.

Method for forming a nickelsilicide FUSI gate

The disclosure provides a semiconductor device and method of manufacture therefore. The method for manufacturing the semiconductor device, in one embodiment, includes forming a layer of gate electrode material over a layer of gate dielectric material, wherein the layer of gate dielectric material is positioned over a substrate (). This method further includes patterning the layer of gate electrode material and the layer of gate dielectric material into an NMOS gate structure (), wherein the NMOS gate structure () includes an NMOS gate dielectric () and an NMOS gate electrode (). This method further includes forming n-type source/drain regions () within the substrate () proximate the NMOS gate structure (), and siliciding the NMOS gate electrode () to form a silicided gate electrode (). This method additionally includes placing a p-type dopant within the layer of gate electrode material or the NMOS gate electrode () prior to or concurrently with siliciding.

Use of dopants to provide low defect gate full silicidation

A dual workfunction semiconductor device which comprises a first and second control electrode comprising a metal-semiconductor compound, e.g. a silicide or a germanide, and a dual workfunction semiconductor device thus obtained are disclosed. In one aspect, the method comprises forming a blocking region for preventing diffusion of metal from the metal-semiconductor compound of the first control electrode to the metal-semiconductor compound of the second control electrode, the blocking region being formed at a location where an interface between the first and second control electrodes is to be formed or is formed. By preventing metal to diffuse from the one to the other control electrode the constitution of the metal-semiconductor compounds of the first and second control electrodes may remain substantially unchanged during e.g. thermal steps in further processing of the device.

Dual workfunction semiconductor device

A semiconductor device is disclosed that comprises a fully silicided electrode formed of an alloy of a semiconductor material and a metal, a workfunction modulating element for modulating a workfunction of the alloy, and a dielectric in contact with the fully silicided electrode. At least a part of the dielectric which is in direct contact with the fully silicided electrode comprises a stopping material for substantially preventing the workfunction modulating element from implantation into and/or diffusing towards the dielectric. A method for forming such a semiconductor device is also disclosed.

Semiconductor device with reduced diffusion of workfunction modulating element

Low work function metals for use as gate electrode in nMOS devices are provided. The low work function metals include alloys of lanthanide(s), metal and semiconductor. In particular, an alloy of nickel-ytterbium (NiYb) is used to fully silicide (FUSI) a silicon gate. The resulting nickel-ytterbium-silicon gate electrode has a work function of about 4.22 eV.

Method of forming a Yb-doped Ni full silicidation low work function gate electrode for n-MOSFET

A method for manufacturing a MOSFET device with a fully silicided (FUSI) gate is described. This method may be used to prevent formation of shorts between the FUSI gate and a contact to a source and/or a drain region. In particular, the method discloses the formation of an expansion volume above a gate dielectric. The volume is designed to substantially contain the fully silicided gate.

Method for forming a fully silicided gate and devices obtained thereof

A polysilicon layer of a gate structure is covered by an implant blocking layer (e.g., silicon nitride). The implant blocking layer blocks introduction of implanted dopants while implanting an initial dose of first conductivity type dopant (e.g., for drain extension regions). The implant blocking layer is then removed and an additional dose of first conductivity type dopant in implanted to form the main source/drain regions. Then, metal is deposited and reacted to form a conductive silicide.

Method to improve silicide formation on polysilicon

A method to enhance the formation of nucleation sites on at least one narrow silicon structure comprises the step: forming at least one nucleation region ( ): masking the at least one narrow silicon structure ( ) with a mask ( ); treating the at least one nucleation region ( ) to enhance an ability of said region to form C54 nucleation sites; and removing the mask from the at least one narrow silicon structure ( ). In another embodiment, a silicon device capable of undergoing a phase transformation comprises at least one narrow silicon structure ( ) formed of TiSi ; and at least one nucleation region ( ) attached to the at least one narrow silicon region ( ), said at least one nucleation region ( ) having a width which is greater than a width of said at least one narrow silicon structure ( ) and said at least one nucleation region ( ) capable of generating a high density of C54 nucleation sites such that said high density of nucleation sites causes a phase transformation ( ) to propagate along the at least one silicon structure ( ).

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Waterloo, Belgium

Jorge Adrian Kittl