Samsung Electronics Co., Ltd.

Joonseok Oh

Changbo Lee

Byunglyul Park

YoungMin Kim

Yoonyoung Jeon

Dongheon Kang

A semiconductor package may include at least one first rewiring structure, the at least one first rewiring structure including a plurality of first insulating layers vertically stacked and a plurality of first rewiring patterns included in the plurality of first insulating layers, at least one semiconductor chip on the at least one first rewiring structure, and at least one molding layer covering the at least one semiconductor chip, wherein each of the plurality of first rewiring patterns includes, a first conductive pattern, the first conductive pattern including a curved upper surface, and a first seed pattern covering a side surface and a lower surface of the first conductive pattern, and each of the first seed patterns of the plurality of first rewiring patterns having a same shape.

Semiconductor package

This invention provides a fan-out semiconductor package, the fan-out semiconductor package includes a frame including one or more insulating layers and having a penetration portion, a semiconductor chip disposed in the penetration portion of the frame and having a connection pad, a connection structure disposed on a lower side of the frame and the semiconductor chip and including a redistribution layer, a first encapsulant covering a back surface of the semiconductor chip and a first region of a top surface of an uppermost insulating layer among the one or more insulating layers of the frame and extending between a sidewall of the penetration portion and a side surface of the semiconductor chip, and a second encapsulant covering a second region of the top surface of the uppermost insulating layer among the one or more insulating layers of the frame and being in contact with a side surface of the first encapsulant on the frame.

Fan-out semiconductor package

A fan-out type semiconductor package may include a frame, a semiconductor chip, a lower photoimageable dielectric (PID), a lower redistribution layer (RDL), a molding member, a first upper RDL, an upper PID and a second upper RDL. The frame may include an insulation substrate having a cavity and a middle RDL formed through the insulation substrate, with the semiconductor chip arranged in the cavity. The first upper RDL may be arranged on an upper surface of the insulation substrate. The first upper RDL may be connected to an upper end of the middle RDL. The upper PID may be formed on upper surfaces of the frame, the semiconductor chip and the molding member. The second upper RDL may be formed in the upper PID. A photolithography process may be applied to the upper PID so that the second upper RDL formed on the upper PID may have a fine pattern.

Growing community of inventors

Suwon-si, South Korea

Joonseok Oh