Samsung Electronics Co., Ltd.

Joon-Soo Park

Ji-young Lee

Gi-Sung Yeo

Sang-Gyun Woo

Han-Ku Cho

Jeong-lim Nam

Kukhan Yoon

Cheolhong Kim

Seokwoo Nam

Cha-won Koh

Tae-young Kim

Jongchul Park

Sang-Jin Kim

Cha-Won Koh

Joon Hyuk Kim

Byeong-Soo Kim

Byeong-soo Kim

Cheol-Kyu Lee

Jun-Ho Yoon

Heung-Sik Park

Methods of forming fine patterns are provided. The methods may include forming first hard mask patterns extending in a first direction on a lower layer, forming second hard mask patterns filling gap regions between the first hard mask patterns, forming first mask patterns extending in a second direction perpendicular to the first direction on the first and second hard mask patterns, etching the first hard mask patterns using the first mask patterns as etch masks to form first openings, forming second mask patterns filling the first openings and extending in the second direction, and etching the second hard mask patterns using the second mask patterns as etch masks to form second openings spaced apart from the first openings in a diagonal direction with respect to the first direction.

Methods for forming fine patterns of a semiconductor device

A method may include forming first hard mask patterns and second hard mask patterns extending in a first direction and repeatedly and alternately arranged on a lower layer, forming third mask patterns extending in a second direction perpendicular to the first direction on the first and second hard mask patterns, etching the first hard mask patterns using the third mask patterns to form first openings, forming filling patterns filling the first openings and gap regions between the third mask patterns, forming spacers on both sidewalls of each of the filling patterns, after removing the third mask patterns, and etching the second hard mask patterns using the filling patterns and the spacers to form second openings.

A method of forming hard mask employs a double patterning technique. A first hard mask layer is formed on a substrate, and a first sacrificial pattern is formed on the first hard mask layer by photolithography. Features of the first sacrificial pattern are spaced from one another by a first pitch. A second hard mask layer is then formed conformally on the first sacrificial pattern and the first hard mask layer so as to delimit recesses between adjacent features of the first sacrificial pattern. Upper portions of the second hard mask layer are removed to expose the first sacrificial pattern, and the exposed first sacrificial pattern and the second sacrificial pattern are removed. The second hard mask layer and the first hard mask layer are then etched to form a hard mask composed of residual portions of the first hard mask layer and the second hard mask layer. A fine pattern of a semiconductor device, such as a trench isolation region or a pattern of contact holes, can be formed using the hard mask as an etch mask.

Method of forming a hard mask and method of forming a fine pattern of semiconductor device using the same

A method of forming a fine pattern of a semiconductor device using a fine pitch hard mask is provided. A first hard mask pattern including first line patterns formed on an etch target layer of a substrate with a first pitch is formed. A first layer including a top surface where a recess is formed between adjacent first line patterns is formed. A second hard mask pattern including second line patterns within the recess is formed. An anisotropic etching process is performed on the first layer using the first and the second line patterns as an etch mask. Another anisotropic etching process is performed on the etch target layer using the first and the second hard mask patterns as an etch mask.

Method of forming pattern using fine pitch hard mask

Semiconductor devices with an improved overlay margin and methods of manufacturing the same are provided. In one aspect, a method includes forming a buried bit line in a substrate; forming an isolation layer in the substrate to define an active region, the isolation layer being parallel to the bit line without overlapping the bit line; and forming a gate line including a gate pattern and a conductive line by forming the gate pattern in the active region and forming a conductive line that extends at a right angle to the bit line across the active region and is electrically connected to the gate pattern disposed thereunder. The gate pattern and the conductive line can be integrally formed.

Semiconductor device with improved overlay margin and method of manufacturing the same

A method of fabricating a semiconductor device is provided. The method can include forming a hard mask film including lower and upper hard mask films on a substrate in which an active region and an isolation region are defined and patterning the hard mask film to provide a hard mask pattern partially exposing the active region and the isolation region. An etchant can be applied to the active and isolation regions using the hard mask pattern as an etching mask to form a trench in the active region of the substrate while avoiding substantially etching the isolation region exposed to the etchant and a gate can be formed on the trench.

Methods of forming semiconductor devices using selective etching of an active region through a hardmask

A method of forming a small pitch pattern using double spacers is provided. A material layer and first hard masks are used and characterized by a line pattern having a smaller line width than a separation distance between adjacent mask elements. A first spacer layer covering sidewall portions of the first hard mask and a second spacer layer are formed, and spacer-etched, thereby forming a spacer pattern-shaped second hard mask on sidewall portions of the first hard mask. A portion of the first spacer layer between the first hard mask and the second hard mask is selectively removed. The material layer is selectively etched using the first and second hard masks as etch masks, thereby forming the small pitch pattern.

Method of forming small pitch pattern using double spacers

There are provided methods of performing a photolithography process for forming asymmetric semiconductor patterns and methods of forming a semiconductor device using the same. These methods provide a way of forming asymmetric semiconductor patterns on a photoresist layer through two exposure processes. To this end, a semiconductor substrate is prepared. A planarized insulating interlayer and a photoresist layer are sequentially formed on the overall surface of the semiconductor substrate. A first semiconductor pattern of a photolithography mask is transferred to the photoresist layer, thereby forming a photoresist pattern on the photoresist layer. A second semiconductor pattern of a second photolithography mask is continuously transferred to the photoresist layer, thereby forming a second photoresist pattern on the photoresist layer. An etching process is performed on the planarized insulating interlayer to expose the semiconductor substrate, using the first photoresist pattern and the second photoresist pattern as etch masks.

Methods of performing a photolithography process for forming asymmetric patterns and methods of forming a semiconductor device using the same

A multiple exposure system and a multiple exposure method using the same enhance the resolution of the image of the mask pattern transferred to a substrate. The system includes NA controllers that provide excellent resolution with respect to the directions of the short axis and long axis of the mask pattern. In one form of the method, a first exposure process is performed using a first NA controller that provides excellent resolution with respect to the direction of the short axis of the mask pattern and subsequently, a second exposure process is performed using a second NA controller that provides excellent resolution with respect to the direction of the long axis of the mask pattern. Alternatively, the first exposure process and the second or high order exposure process can be sequentially performed using the first and second NA controllers simultaneously.

Multiple exposure apparatus and multiple exposure method using the same

A stereoscopic image display apparatus displays a stereoscopic image using only a single projector. The apparatus includes a photography section for sensing a left image and a right image of an object and converting the left and right images into respective first and second television signals. The first and second television signals are received by a receiving section which then provides the signals to a double-scanning section. The double-scanning section scans the left and right image signals received from the receiving section at a doubled horizontal scan frequency to produce a left double-scanned image signal and a right double-scanned image signal. A multiplexing section then alternately selects the left and right double-scanned image signals at a switching speed of the doubled horizontal frequency to thereby produce a single, multiplexed double-scanned image signal. A projection type display section projects the multiplexed double-scanned image signal onto a single display screen.

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Seongnam-si, South Korea

Joon-Soo Park