Infineon Technologies Ag

Other

Infineon Technologies North America Corp.

Jonghee Han

Jung Pill Kim

Alessandro Minzoni

Joonho Kim

Torsten Partsch

Stephen Michael Camacho

Alexander George

A duty cycle corrector includes a first controllable delay configured to delay a first signal to provide a second signal, a second controllable delay configured to delay the second signal to provide a third signal, a circuit configured to adjust the first controllable delay and the second controllable delay to phase lock the third signal to the first signal, and a phase mixer configured to phase mix the first signal and the third signal to provide a fourth signal.

Duty cycle corrector

A synchronous output signal generated by an integrated circuit (IC) component is synchronized to an applied clock signal for each individual IC component. A variable feedback delay in the IC component is incrementally altered to alter the phase skew between the clock signal and the output signal. The relative phase order of the clock and output signals is monitored in the IC component. In response to detecting a swap in the relative phase order of the clock and output signals, the variable feedback delay ceases to be altered. In some embodiments, the IC component may be a SDRAM component.

System and method to synchronize signals in individual integrated circuit components

A duty cycle corrector includes a first controllable delay, a second controllable delay, a phase detector, and a compensation circuit. The first controllable delay is configured to delay a first signal to provide a second signal. The second controllable delay is configured to delay the second signal to provide a third signal. The phase detector is configured to adjust the first controllable delay and the second controllable delay to phase lock the third signal to the first signal. The compensation circuit is configured to compensate for a mismatch between the first controllable delay and the second controllable delay to provide a fourth signal in response to the first signal and a fifth signal approximately 180 degrees out of phase with the fourth signal in response to the second signal.

A duty cycle corrector, including a first, second circuit and a third circuit is disclosed. The third circuit is configured to obtain a threshold value in response to charge flow that is regulated by the first circuit and the second circuit, wherein the first circuit is configured to receive a clock signal and change the charge flow at a first transition of the clock signal. The second circuit is configured to change the charge flow at a second transition of the clock signal. The first circuit and the second circuit are configured to change the charge flow in response to obtaining the threshold value.

A duty cycle corrector comprising a first circuit and a second circuit. The first circuit is configured to receive a clock signal having a first phase and a second phase and to obtain a first threshold value based on the length of the first phase and part of the second phase and provide a first pulse and response to the first threshold value. The second circuit is configured to receive the clock signal and to obtain a second threshold value based on the length of the second phase and part of the first phase and provide a second pulse in response to the second threshold value. The time between the start of the first pulse and the start of the second pulse is substantially one half clock cycle.

Input circuit configurations that reduce the amount of input signal jitter caused by a common input signal return path, methods and circuits utilizing the same are provided. Input signal return path noise may be decoupled from the power for receiver circuits, for example, by utilizing separate power supply lines, such as Vand V, as input signal return path.

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Buffer circuits and techniques that reduce skew between rising and falling times of output data as process conditions vary are provided. One or more process-dependent current sources may be utilized to compensate for process variations by supplementing the current drive of transistors used to precharge (PMOS) or discharge (NMOS) an output node of a secondary (e.g., inverter) stage of the buffer circuit.

Low rise/fall skewed input buffer compensating process variation

A duty cycle detector comprising a first circuit configured to receive clock cycles including a first level and a second level. The first circuit is configured to obtain a first value based on the length of the first level and to obtain second and third values based on the length of the second level. The first value is compared to the second and the third values to determine a duty cycle range of the clock cycles.

Duty cycle detector with first, second, and third values

An input circuit including a first circuit, a second circuit, and a third circuit. The first circuit is configured to receive a first signal and a second signal and to sample the first signal via the second signal and provide signal samples of the first signal. The second circuit is configured to receive a third signal and the signal samples and to update a second circuit output signal via the third signal and provide the updated second circuit output signal. The third circuit is configured to receive a clock signal and the second signal and to provide the third signal. The third circuit is also configured to synchronize edges in the third signal to edges in the second signal and edges in the clock signal.

Input circuit having updated output signal synchronized to clock signal

A circuit for latching data into a memory includes a receiver, a delay, and a selector. The receiver is configured for receiving a data signal, and the delay is configured to delay the data signal to provide a delayed data signal. The selector is configured to receive the delayed data signal, a data strobe signal, and an inverted data strobe signal and provide a first strobe signal and a second strobe signal in response to the delayed data signal, the data strobe signal, and the inverted data strobe signal. Rising edge data is latched into the memory in response to the first strobe signal and falling edge data is latched into the memory in response to the second strobe signal.

Memory with data latching circuit including a selector

A buffer circuit includes a differential amplifier, a buffering inverter, and a reference voltage monitoring circuit. The differential amplifier has a reference voltage and a current source as inputs. The buffering inverter has an output of the differential amplifier as an input. The reference voltage monitoring circuit includes two transistors and a second current source. An output of the reference voltage monitoring circuit is connected to the buffering inverter so as to minimize an effect of a variation in the value of the reference voltage on signal propagation delay times. The buffer circuit can further include a driver circuit with a comparator. A method of managing signal propagation delays includes providing a differential amplifier, providing at least one buffering inverter, and providing a reference voltage monitoring circuit. The reference voltage monitoring circuit can maintain signal propagation delays as a reference voltage varies.

Input buffer circuit including reference voltage monitoring circuit

A random access memory includes a first circuit configured to receive a strobe signal and provide pulses in response to transitions in the strobe signal, and a second circuit configured to receive the strobe signal to latch data into the second circuit in response to the strobe signal, and to receive the pulses to re-latch the latched data into the second circuit after the transitions in the strobe signal. The first circuit includes an enable circuit configured to provide an enable signal and a buffer circuit configured to receive the strobe signal and the enable signal and provide the pulses in response to the enable signal and the strobe signal. The enable circuit is configured to receive the pulses from the buffer circuit and stop providing the enable signal to the buffer circuit in response to receiving the pulses.

Random access memory with post-amble data strobe signal noise rejection

A method and circuit configuration for digitizing data and control signals using an input buffer in a dynamic random access memory (DRAM) device. In one embodiment, the input buffer includes buffer modules having a differential amplifier with a first input responsive to an input signal and a second input responsive to a reference voltage, a common source stage, and an output stage and a source of a bias voltage controlling impedance of the common source stage, wherein the reference voltage defines the amplitude of the bias voltage.

Method and circuit configuration for digitizing a signal in an input buffer of a DRAM device

Embodiments of the present invention are illustrated in a random access memory. In one embodiment, a random access memory comprises an array of memory cells, a write circuit, and an input buffer configured to receive data and pass the received data to the write circuit that writes the received data into the array of memory cells. The input buffer comprises a differential amplifier configured to receive the data and in response to the received data supply a first signal and a second signal that is the compliment of the first signal. The input buffer also comprises a first transistor configured to be controlled by the first signal and a second transistor configured to be controlled by the second signal. The first transistor and the second transistor are turned on to provide a current path through the first transistor and the second transistor to change the first signal in response to a transition in the received data.

Input buffer with differential amplifier

Sensing operations involving a first array of bit line sense amplifiers (BLSAs) may be powered by an upper reference voltage and a first intermediate voltage and the first array may be precharged to a voltage level therebetween. Sensing operations involving a second array of BLSAs may be powered by a second intermediate voltage (greater than the first intermediate voltage) and a lower reference voltage and the second array may be precharged to a voltage level therebetween. After precharge, charge may be transferred from a second power line of the first array to a first power line of the second array. Subsequently, the second power line of the first array may be coupled to a power supply node at the first intermediate voltage level and the first power line of the second array may be coupled to a power supply node at the second intermediate voltage level.

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Cary, NC, United States of America

Jonghee Han