Samsung Electro-mechanics Co., Ltd.

Korea Advanced Institute of Science and Technology

Jong Ok Ha

Jeong Hoon Kim

Byeong Hak Jo

Shinichi Iizuka

Young Wong Jang

Youn Suk Kim

Hyun Paek

Yong Hoon Lee

Kwang Du Lee

Sang Il Lee

Eui Rim Jeong

Soon Il Hong

Ho Kwon Yoon

Jae Hyouck Choi

Min Hyun Kim

Kyu Jin Choi

Seong Jin Kim

Suk Chan Kang

Kyung Hee Hong

Iizuka Shinichi

Soon Chan Park

Young Wook Sirl

Kwang Pyo Lee

An apparatus that generates and limits a bias current of a power amplifier is provided. The apparatus includes a bias current circuit that generates a bias current to bias the power amplifier, and critically limit an increase in bias current, and a band gap reference circuit that provides a reference voltage or a reference current to the bias current circuit. The bias current circuit is configured to critically limit the increase in bias current, as a first bias transistor that generates the bias current is converted from a triode region to a saturation region, based on the reference voltage or the reference current.

Power amplifier with bias current generating and bias current limiting apparatus

A bias timing control circuit includes a current source, a bias switch circuit, a duty cycle sensing circuit, and a switching control circuit. The bias switch circuit includes a first path switch, connected between an output node of the current source and a bias amplifying circuit, and a second path switch, connected between the output node of the current source and a temperature compensation circuit. The duty cycle sensing circuit is configured to generate a timing control signal based on a duty cycle of a transmission enable signal. The switching control circuit is configured to control a first turn-on time of the first path switch during an initial startup period, and a second turn-on time of the second path switch during a normal driving period subsequent to the initial startup period to adjust a warm-up time of a power amplifying circuit based on the timing control signal.

Amplifying device with bias timing control circuit based on duty cycle

An amplifying apparatus is provided. The amplifying apparatus comprises an amplifying circuit comprising a power amplifier and a bias circuit, the bias circuit is configured to detect an ambient temperature of the power amplifier to output a temperature voltage and regulate an internal current based on an input control signal to supply a bias current obtained by the regulation to the power amplifier; and a temperature control circuit that generates the control signal based on the temperature voltage during initial driving from a transmission mode starting point in time to an input point in time at which an input signal is input and outputting the control signal to the amplifying circuit.

Amplifying apparatus with improved linearity

A power amplifier device includes a bias circuit to generate a startup current, which is based on an internal voltage and a startup voltage, during a startup time prior to a steady driving time point, and to generate a bias current, which is based on the internal voltage, after the steady driving time point, and a startup circuit to supply the bias circuit with the startup voltage during the startup time.

Power amplifier device with improved response speed

A bias circuit includes a current source to generate a reference current, a temperature compensation portion in an off-state in an initial start period in response to a first control signal, and in an on-state in a normal driving period, subsequent to the initial start period, and to receive a first current of the reference current, and a bias output portion to generate a warm up current based on the reference current in the initial start period and to generate a bias current based on a second current, which is lower than the reference current by an amount of the first current, in the normal driving period.

Bias circuit and power amplifier for improving linearity

A power amplifier apparatus, includes an envelope tracking (ET) current bias circuit configured to generate a first ET bias current by calculating a direct current DC, based on a reference voltage, and an ET current, based on an ET voltage, according to an envelope of an input signal; and a power amplifier circuit having a bipolar junction transistor supplied with the first ET bias current and a power voltage to amplify the input signal, wherein an average current of the first ET bias current is controlled to be substantially constant.

Adaptive multiband power amplifier apparatus

An envelope tracking (ET) bias circuit includes a detection circuit configured to select an ET operation voltage input through a first input terminal of the detection circuit, or an envelope signal detected from a radio frequency (RF) signal input through a second input terminal of the detection circuit, in response to a first control signal, to and output he selected one of the ET operation voltage and the envelope signal as a detection signal; an amplification circuit configured to amplify the detection signal, and output the amplified detection signal; and a bias output circuit configured to generate an ET bias current based on the amplified signal, and output the generated ET bias current.

Envelope tracking bias circuit and power amplifying device

An envelope tracking (ET) bias circuit includes an envelope tracking (ET) bias circuit includes an envelope detection circuit, an envelope amplifier circuit, and an envelope output circuit. The envelope detection circuit is configured to detect an envelope of an input signal, and output an envelope signal based on the detected envelope of the input signal. The envelope amplifier circuit is configured to differentially amplify the envelope signal in response to a first control signal and cancel a direct current (DC) offset of the envelope signal to output an amplified signal from which the DC offset is canceled. The envelope output circuit is configured to generate an ET bias current by selecting either one of a negative signal of the amplified signal and a positive signal of the amplified signal in response to a second control signal.

Envelope tracking bias circuit

An envelope tracking (ET) current bias circuit includes a rectifying circuit, a phase compensation circuit, and a voltage/current conversion circuit. The rectifying circuit is configured to detect an envelope voltage from a radio frequency (RF) signal. The phase compensation circuit is configured to compensate for a phase of the envelope voltage in which the phase thereof is delayed in the rectifying circuit to output a phase compensated enveloped voltage. The voltage/current conversion circuit is configured to convert the phase compensated envelope voltage into an ET bias current.

Envelope tracking current bias circuit and power amplifying device

A control buffer circuit includes a voltage detection circuit configured to detect whether a received voltage is a negative voltage or a ground voltage and provide a voltage detection signal based on a result of the detecting, and a buffer circuit configured to provide a switching signal based on the voltage detection signal, wherein the switching signal comprises a positive voltage as a switching-on level voltage and includes one or more of the ground voltage and the negative voltage as a switching-off level voltage.

Control buffer circuit and radio frequency switch for dual mode operation

A reference current generating circuit includes a current source circuit configured to generate a reference current based on an internal resistor; and a compensation circuit configured to comprise a first compensation circuit comprising a first compensation resistor and a second compensation resistor, and the first compensation resistor and the second compensation resistor are configured to convert the reference current into a first output current and compensate for process variation of the current source circuit.

Reference current generating circuit with process variation compensation

An envelope-tracking current bias circuit includes a first rectifying circuit, a second rectifying circuit, and a first arithmetic circuit. The first rectifying circuit is configured to detect an envelope of an input signal, and provide an envelope detection signal comprising a first direct current (DC) offset voltage. The second rectifying circuit is configured to provide a second DC offset voltage corresponding to the first DC offset voltage. The first arithmetic circuit is configured to provide an envelope signal in which the first DC offset voltage is reduced through subtraction between the envelope detection signal and the second DC offset voltage.

Envelope-tracking current bias circuit with offset cancellation function

A power amplifying apparatus includes a power circuit configured to generate operating power, a random pulse generation circuit configured to be supplied with the operating power and to generate a pulse width modulation signal of which a pulse width is randomly changed over time using an input radio frequency (RF) signal, and a charge pump circuit configured to be supplied with the operating power and to randomly perform a switching operation according to the pulse width modulation signal to generate a negative voltage.

Power amplifying apparatus with spurious signal reduction function

An envelope tracking (ET) current bias circuit comprises an envelope detection circuit detecting an ET voltage from an input signal; a first voltage/current converting circuit converting a reference voltage into a direct current (DC) current and adjusting the DC current according to a first control signal; a second voltage/current converting circuit converting the ET voltage into an ET current, adjusting the ET current according to a second control signal, and removing a DC offset current from the ET current to provide an offset compensated ET current; and an arithmetic circuit calculating levels of the offset compensated ET current and the DC current to generate an ET bias current.

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Suwon-si, South Korea

Jong Ok Ha