Applied Materials, Inc.

Jong Mun Kim

Chentsau Chris Ying

Daisuke Shimizu

Minrui Yu

Srinivas D Nemani

Kenny Linh Doan

Ellie Y Yieh

Mahendra Pakala

He Ren

Chando Park

Jaesoo Ahn

Mang-Mang Ling

Jairaj Joseph Payyapilly

Mehul B Naik

Huixiong Dai

Bryan Y Pu

Sahil Patel

Christopher S Ngai

Wenhui Wang

Lin Xue

Sergio Fukuda Shoji

Jingbao Liu

Maximillian Clemons

Hamid Noorbakhsh

Ajit Balakrishna

Thomas Jongwan Kwon

Erica Chen

Ajey M Joshi

Katsumasa Kawasaki

Cheng Pan

Biao Liu

Judy Wang

Li Ling

Jason Della Rosa

Yuju Huang

Embodiments of the present disclosure generally include spin-orbit torque magnetoresistive random-access memory (SOT-MRAM) devices and methods of manufacture thereof. The SOT-MRAM devices described herein include an SOT layer laterally aligned with a magnetic tunnel junction (MTJ) stack and formed over a trench in an interconnect. Thus, the presence of the SOT layer outside the area of the MTJ stack is eliminated, and electric current passes from the interconnect to the SOT layer by SOT-interconnect overlap. The devices and methods described herein reduce the formation of shunting current and enable the MTJ to self-align with the SOT layer in a single etching process.

Spin-orbit torque MRAM structure and manufacture thereof

Embodiments of the present disclosure generally relate to a method for forming an opening using a mask. In one embodiment, a method includes forming a mask on a feature layer. The method includes forming a first opening in the mask to expose a portion of the feature layer. The method further includes forming a carbon layer on the mask and the exposed portion of the feature layer. The method also includes removing portions of the carbon layer and a portion of the exposed portion of the feature layer in order to form a second opening in the feature layer.

Carbon layer covered mask in 3D applications

Exemplary methods of etching semiconductor substrates may include flowing a halogen-containing precursor into a processing region of a semiconductor processing chamber. The processing region may house a substrate having a conductive material and an overlying mask material. The conductive material may be characterized by a first surface in contact with the mask material, and the mask material may define an edge region of the conductive material. The methods may include contacting the edge region of the conductive material with the halogen-containing precursor and the oxygen-containing precursor. The methods may include etching in a first etching operation the edge region of the conductive material to a partial depth through the conductive material to produce a footing of conductive material protruding along the edge region of the conductive material. The methods may also include removing the footing of conductive material in a second etching operation.

Damage free metal conductor formation

Embodiments of the disclosure provide methods and apparatus for fabricating magnetic tunnel junction (MTJ) structures on a substrate for MRAM applications. In one embodiment, a method for forming a magnetic tunnel junction (MTJ) device structure includes performing a patterning process by an ion beam etching process in a processing chamber to pattern a film stack disposed on a substrate, wherein the film stack comprises a reference layer, a tunneling barrier layer and a free layer disposed on the tunneling barrier, and determining an end point for the patterning process.

Methods for etching a structure for MRAM applications

Methods for removing residuals after a selective deposition process are provided. In one embodiment, the method includes performing a selective deposition process to form a metal containing dielectric material at a first location of a substrate and performing a residual removal process to remove residuals from a second location of the substrate.

Residual removal

Methods for dry plasma etching thin layers of material including Cu(In, Ga)Se, e.g., CIGS material on semiconductor substrates are provided. A method of etching a CIGS material layer such as copper indium gallium selenide film, includes: flowing an etching gas including a mixture of gases into a process chamber having a substrate disposed therein, the substrate including a copper indium gallium selenide layer having a patterned film stack disposed thereon, the patterned film stack covering a first portion of the copper indium gallium selenide layer and exposing a second portion of the copper indium gallium selenide layer; and contacting the copper indium gallium selenide layer with the etching gas to remove the second portion and form one or more copper indium gallium selenide edges of the first portion.

Method of etching copper indium gallium selenide (CIGS) material

Methods and apparatus for processing a substrate and etching a nickel silicide layer are provided herein. In some embodiments, a method of etching a nickel silicide film in a semiconductor device include: contacting a nickel silicide film disposed on a substrate in a process chamber with an etching gas sufficient to form one or more soluble or volatile products in order to reduce or eliminate re-deposition of products formed from the nickel silicide film upon the nickel silicide film.

Methods of patterning nickel silicide layers on a semiconductor device

Multilayered stacks having layers of silicon interleaved with layers of a dielectric, such as silicon dioxide, are plasma etched with non-corrosive process gas chemistries. Etching plasmas of fluorine source gases, such as SFand/or NFtypically only suitable for dielectric layers, are energized by pulsed RF to achieve high aspect ratio etching of silicon/silicon dioxide bi-layers stacks without the addition of corrosive gases, such as HBr or Cl. In embodiments, a mask open etch and the multi-layered stack etch are performed in a same plasma processing chamber enabling a single chamber, single recipe solution for patterning such multi-layered stacks. In embodiments, 3D NAND memory cells are fabricated with memory plug and/or word line separation etches employing a fluorine-based, pulsed-RF plasma etch.

Silicon dioxide-polysilicon multi-layered stack etching with plasma etch chamber employing non-corrosive etchants

Embodiments of the present invention provide apparatus and methods for reducing non-uniformity and/or skews during substrate processing. One embodiment of the present invention provides a flow equalizer assembly for disposing between a vacuum port and a processing volume in a processing chamber. The flow equalizing assembly includes a first plate having at least one first opening, and a second plate having two or more second openings. The first and second plates define a flow redistributing volume therebetween, and the at least one first opening and the two or more second openings are staggered.

Recursive pumping for symmetrical gas exhaust to control critical dimension uniformity in plasma reactors

An article having alternating oxide layers and nitride layers is etched by an etch process. The etch process includes providing a first gas comprising CFHin a chamber of an etch reactor, ionizing the CFHcontaining gas to produce a plasma comprising a plurality of ions, and etching the article using the plurality of ions.

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One or more openings in an organic mask layer deposited on a first insulating layer over a substrate are formed. One or more openings in the first insulating layer are formed through the openings in the organic mask using a first iodine containing gas. An antireflective layer can be deposited on the organic mask layer. One or more openings in the antireflective layer are formed down to the organic mask layer using a second iodine containing gas. The first insulating layer can be deposited on a second insulating layer over the substrate. One or more openings in the second insulating layer can be formed using a third iodine containing gas.

Maintaining mask integrity to form openings in wafers

Implementations described herein generally relate to semiconductor manufacturing and more particularly to the process of plasma etching an amorphous carbon layer. In one implementation, a method of etching a feature in an amorphous carbon layer is provided. The method comprises transferring a substrate including a patterned photoresist layer disposed above the amorphous carbon layer into an etching chamber, exposing the amorphous carbon layer to a fluorine-free etchant gas mixture including a fluorine-free halogen source gas and a passivation source gas and etching the amorphous carbon layer with a plasma of the fluorine-free etchant gas mixture. It has been found that plasma etching with a fluorine-free halogen based gas mixture reduces the formation of top critical dimension clogging oxides.

Plasma etch processes for opening mask layers

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San Jose, CA, United States of America

Jong Mun Kim