Samsung Electronics Co., Ltd.

Jong-Heui Song

Jun Hyuk Seo

Jong-chul Park

Min-Chul Chae

Tae-hyuk Ahn

Jae-Seung Hwang

Jong-Hyuk Kim

Dae-Keun Kang

Hyuk-Jin Kwon

Yung-Jun Kim

Yong-Sun Ko

Young-Woo Park

Sang-sup Jeong

Woo-Sik Kim

Yun-seung Kang

Jun Ho Seo

Young-Mi Lee

Tae-ryong Kim

Se-Hyeong Lee

Dong-yun Kim

Woo-Jin Cho

Du-Hyun Cho

Tae-Woo Kang

Seung-Joo Yoo

Ho Ko

Chung-Howan Kim

Min-Woong Choi

A dual damascene structure and a method of forming a dual damascene structure are disclosed. The dual damascene structure includes an insulation member, a single crystal member and a filling member. The insulation member has an opening having a dual damascene shape. The filling member is formed on a side face of the opening. The single crystal member contacts the filling member. The single crystal member fills up the opening. In order to form a dual damascene structure, an insulating member having an opening partially filled with a preliminary single crystal member is formed. The filling member is formed on a side face of the opening. The preliminary single crystal member epitaxially grows to fill up the opening. Because the filling member is positioned between the single crystal member and the insulation member, void formation may be reduced between the single crystal member and the insulation member.

Methods of forming dual damascene structures

In methods of forming a trench, first patterns separated from each other by a first width and second patterns separated from each other by a second width are formed on a substrate. The second width is wider than the first width. The substrate is etched using the first patterns and the second patterns to form a first trench having a first depth and a preliminary second trench having a second depth. A sacrificial layer is formed to fill up a space between the first patterns. The substrate is etched using the sacrificial layer to form a second trench having a third depth deeper than the second depth.

Methods of manufacturing a semiconductor device using a layer suspended across a trench

A method of fabricating a semiconductor device including a fin field effect transistor (Fin-FET) includes forming sacrificial bars on a semiconductor substrate, patterning the sacrificial bars to form sacrificial islands on the semiconductor substrate, forming a device isolation layer to fill a space between the sacrificial islands, selectively removing the sacrificial islands to expose the semiconductor substrate below the sacrificial islands, and anisotropically etching the exposed semiconductor substrate using the device isolation layer as an etch mask to form a recessed channel region. The recessed channel region allows the channel width and channel length of a transistor to be increased, thereby reducing the occurrence of short channel effects and narrow channel effects in highly integrated semiconductor devices.

Methods of fabricating semiconductor device including fin-fet

In a phase change memory, an interlayer insulating layer is disposed on a substrate. A heater plug includes a lower portion disposed in a contact hole penetrating the interlayer insulating layer and an upper portion protruding upward over the top surface of the interlayer insulating layer. A phase change pattern is disposed on the interlayer insulating layer to cover the top surface and the side surface of the protruding portion of the heater plug. An insulating spacer is interposed between the phase change pattern and the side surface of the protruding portion of the heater plug. A capping electrode is disposed on the phase change pattern.

Phase change memory devices and methods for fabricating the same

A method according to some embodiments of the invention includes defining an active region by forming a trench device isolation region on an integrated substrate, forming a mask pattern that exposes a channel sub-region of the active region and the trench device isolation region adjacent to the channel sub-region, etching the trench device isolation region, which is exposed by the mask pattern, to be recessed to a first depth using the mask pattern as an etch mask, etching the channel sub-region to form a gate trench having a second depth that is deeper than the first depth using the mask pattern as an etch mask, and forming a recess gate that fills the gate trench.

Method of manufacturing integrated circuit device including recessed channel transistor

Dual damascene structure and methods of forming the same

A MOS transistor with a recessed gate and a method of fabricating the same: The MOS transistor comprises a semiconductor substrate, and a trench isolation layer located in a predetermined region of the semiconductor substrate for defining an active region. The trench isolation layer has a negative slope on at least a lower sidewall thereof. A recessed gate is located in a predetermined region of the active region, and a bottom surface of the recessed gate is placed adjacent the negatively slopped sidewall of the trench isolation layer.

MOS transistor with recessed gate and method of fabricating the same

A method for forming a contact plug formed of polysilicon and a method for manufacturing a semiconductor device using the same are provided. The contact plug is formed by etching back polysilicon which fills a contact hole and is deposited on an interlayer dielectric film using a gas mixture of SF,, CHF,, and CF,, thus planarizing the polysilicon. Also, the contact plug can be made protrude above the interlayer dielectric film by etching the entire surface of the exposed interlayer dielectric film around the polysilicon contact plug formed by etching back the polysilicon. According to the present invention, the degree of planarization of the polysilicon contact plug is improved by etching back the polysilicon using the gas mixture of SF,, CHF,, and CF,. Furthermore, it is possible to prevent contact failure due to the depression of the contact plug by etching the entire surface of the interlayer dielectric film thus causing the contact plug to protrude above the interlayer dielectric film, thereby increasing the plug's contact area and reducing the contact failure.

Method of fabricating a contact in a semiconductor device

A method of forming a low-k dielectric insulating layer includes forming the dielectric insulating layer and then removing hydrogen bonds in the dielectric insulating layer. The dielectric layer as formed is preferably a HSQ film which contains the structure Si--O--H. Hydrogen is removed from the dielectric layer by either: a heat treatment in plasma, an ozone reduction process, an ion implantation process, or electron beam bombardment.

Method of making intermetal dielectric layers having a low dielectric

A plasma etching apparatus is provided having a sealing member coupling an upper electrode to the plasma etching chamber. A peripheral portion of the inner surface of the upper electrode includes a planar surface across both anodized and non-anodized portions of the surface in the peripheral contact region adjacent to the upper portion of the sidewalls of the chamber assembly. A sealing member is positioned between the planar, peripheral portion of the second electrode and the upper portion of the sidewalls to provide a seal therebetween. The anodized portion of the inner surface of the upper electrode may extend over the area adjacent to the opening in the chamber housing and further extend into the peripheral portion beyond the sealing member to reduce the potential for arcing to occur to the non-anodized section during plasma etching operations. Plasma etching apparatus according to the present invention may provide improved sealing, thereby allowing improved control of vacuum level and concentration of processing gas within the plasma etching chamber during etching operations.

Plasma etching apparatus having a sealing member coupling an upper

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Gyeonggi-do, South Korea

Jong-Heui Song