Sandisk Technologies Inc.

Silicon Magnetic Systems

Jong Hak Yuh

Tai-Yuan Tseng

Qui V Nguyen

Yen-Lung Li

Deepanshu Dutta

Kwang-Ho Kim

Muhammad Masuduzzaman

Kenneth Louie

Alexander Chu

Raul-Adrian Cernea

Seungpil Lee

Abhijeet Manohar

Raul Adrian Cernea

Tien-Chien Kuo

Hua-Ling Cynthia Hsu

Jonathan Huynh

Cynthia Hsu

Jixin Yu

Farookh Moogat

Khanh Vinh Nguyen

YenLung Li

Ashish Pancholy

Ohwon Kwon

Gary Austin Gibbs

Anirudh Amarnath

Victor Avila

Disclosed includes a memory device and a method of operating the memory device. A voltage is applied to a word line coupled to first memory transistors of a first plurality of strings of transistors and second memory transistors of a second plurality of strings of transistors. A current flow through one or more of the first plurality of strings of transistors is enabled, while applying the voltage to the word line. A current flow through the second plurality of strings of transistors is disabled by floating source terminals and drain terminals of the second memory transistors, while enabling the current flow through the one or more of the first plurality of strings of transistors.

Select gates separation for improving performance in three-dimensional non-volatile memory

This disclosure provides a method and apparatus for applying a dynamic strobe signal to a plurality of sense modules during programming of an array of memory cells, where a characteristic of the dynamic strobe signal is configured to limit a peak current level through the plurality of sense modules. An example apparatus the array of memory cells, a plurality of bit lines spanning the array of memory cells, and the plurality of sense modules connected to the bit lines. The plurality of sense modules enable sensing of states of memory cells. A controller determines the characteristic of the dynamic strobe signal, where the dynamic strobe signal is varied based on the determined characteristic.

Loop control strobe skew

In one aspect, a voltage is provided as a rectangular waveform in which the duty cycle is varied to provide different effective voltages. These voltages may be applied to various control lines in a memory device such as a word line, bit line and/or source line, in a program, verify, read or erase operation. In some cases, the duty cycle is a function of programming data of a memory cell such as an assigned data state or a programming speed category. The duty cycle could also be a function of a programming phase or other criterion. The duty cycle can be varied by modifying the duration and separation of the pulses of the waveform or by pulse counting, in which a specified number of pulses are passed in a time period.

Pulsed control line biasing in memory

Apparatuses, systems, and methods are disclosed for three-dimensional non-volatile memory. A stack of word line layers includes word lines for a three-dimensional non-volatile memory array. A stack of word line layers may include a plurality of tiers. Word line switch transistors transfer word line bias voltages to the word lines. Word line contact regions couple word line switch transistors to word lines. A word line contact region includes a stepped structure for a tier of word line layers. A level region separates a word line contact region for a first tier from a word line contact region for a second tier.

Word line contact regions for three-dimensional non-volatile memory

A memory system and method for improving write performance in a multi-die environment are disclosed. In one embodiment, a memory system is provided comprising a plurality of memory dies and a controller. The controller is configured to determine a programming status of each of the plurality of memory dies and dynamically adjust a maximum peak current limit of the plurality of memory dies based on the programming status of each of the plurality of memory dies. Other embodiments are provided.

Memory system and method for improving write performance in a multi-die environment

Systems and methods for reducing sensing time for sensing data states stored within a plurality of memory cells are described. In some cases, the ramping of a word line connected to the plurality of memory cells may be delayed until a threshold current corresponding with a particular number of erased memory cells of the plurality of memory cells has been met or exceeded. The threshold current may be compared with a summation of a first set of detection currents corresponding with a first set of memory cells of the plurality of memory cells that have been sensed to be in a conducting state while the word line is set to a voltage level for sensing erased memory cells. The threshold current may be set based on a chip temperature and/or a particular number of bit errors that occurred during a prior sensing operation.

Fast scan to detect bit line discharge time

Apparatuses, systems, and methods are disclosed for accessing non-volatile memory. A bit line is coupled to storage cells for a non-volatile memory element. A sense amplifier is coupled to a bit line. A sense amplifier includes a sense circuit and a bias circuit. A sense circuit senses an electrical property of a bit line for reading data from one or more storage cells, and a bias circuit applies a bias voltage to the bit line for writing data to one or more storage cells. A bias circuit and a sense circuit comprise separate parallel electrical paths within a sense amplifier.

Sense amplifier with program biasing and fast sensing

Sense circuits in a memory device can be pre-charged to different levels in a sensing process to reduce the amount of time used for sensing. During sensing of first and second memory cells, a control circuit pre-charges first and second sense circuits to first and second voltages, respectively. The first and second sense circuits are associated with the first and second memory cells, respectively. Also, during the sensing, a control gate voltage is applied to the first and second memory cells. The control circuit allows the first and second sense node voltages to discharge in a common discharge period and the cells are sensed using a common trip condition. The first and second memory cells are therefore subject to different concurrent verify tests.

Memory device which performs verify operations using different sense node pre-charge voltages and a common discharge period

A method is provided for programming a non-volatile memory. The method includes programming memory cells for even bit lines by programming the memory cells into a plurality of intermediate data states from an erased state, and for each of the intermediate data states, concurrently programming the memory cells to a plurality of target data states. The method also includes programming memory cells for odd bit lines by programming the memory cells into the plurality of intermediate data states from an erased state, and for each of the intermediate data states, concurrently programming the memory cells to the plurality of target data states.

Multi-state programming for non-volatile memory

Methods and devices for sensing non-volatile storage are disclosed. Technology disclosed herein reduces the time for sensing operations of non-volatile storage such as read and program verify. In one embodiment, a kicking voltage is applied to a selected word line during a sensing operation. The kicking voltage may be applied to one end of a selected word line during a transition from a first reference voltage to a second reference voltage. The kicking voltage may help the other end of the word line reach the second reference voltage quickly. Since the bit lines can be sensed after the selected word line has reached the target reference voltage, the time delay prior to sensing of the bit lines may be reduced.

Word line kicking when sensing non-volatile storage

In non-volatile memory devices, a write operation typically consists of an alternating set of pulse and verify operations. After a pulse is applied, the device must be biased properly for an accurate verify, with a selected word-line settled at the desired voltage level. The techniques described here address the problem of a relatively large waiting time at the start of a verify phase of a write operation when the selected word line is moving to its first verify level, while at the same time the non-selected word lines of a NAND type array are ramping up to a read pass level. For the non-selected word lines, during the program pulse, these are set at a first voltage above ground and then, during the verify operation, then are set at the read pass level. Rather than take the non-selected word lines to ground in between, they are instead moved directly from their voltage in the pulse phase directly into their read pass level. This helps to reduce the amount of movement in the selected word line due to capacitive coupling, allowing the preparation of the verify level of a selected word line settings earlier.

Techniques for the fast settling of word lines in NAND flash memory

A memory circuit which is adapted to identify memory cells within a first time interval for a write operation of the circuit and identify the memory cells within a second time interval for a read operation of the circuit is provided. In some cases, the memory circuit may include an address path which includes a different circuit path for the read operations than for the write operations of the circuit. In addition, the memory circuit may include a means for intentionally delaying the identification of the memory cells for the write operation of the circuit. In some cases, the memory circuit may further include a means for intentionally delaying the identification of memory cells for the read operation of the circuit. Alternatively, the memory circuit may be absent a means for intentionally delaying the identification of memory cells for the read operation of the circuit.

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Pleasanton, CA, United States of America

Jong Hak Yuh