Samsung Electronics Co., Ltd.

Hitachi, Ltd.

Hitachi-high-technologies Corporation

Hitachi High-technologies Co.

Jong-bong Park

Hion-suck Baik

Sang-jin Park

Kazutoshi Kaji

Shohei Terada

Eun-ha Lee

Kwang-soo Seol

Tatsumi Hirano

Min-ho Yang

Gyeong-su Park

Se-ahn Song

Ho Young Lee

Jung-Hyun Lee

Hwa-Sung Rhee

Jun-Soo Bae

Ji-Hye Yi

Byung-seo Kim

Woong-chul Shin

Myung-sun Kim

Jung-Yun Won

Hlon-suck Baik

Jang-ho Lee

Yun-chang Park

Provided is an aluminum (Al) doped charge trap layer, a non-volatile memory device and methods of fabricating the same. The charge trap layer may include a plurality of silicon nano dots that trap charges and a silicon oxide layer that covers the silicon nano dots, wherein the charge trap layer is doped with aluminum (Al). The non-volatile memory device may include a substrate including a source and a drain on separate regions of the substrate, a tunneling film on the substrate contacting the source and the drain, the charge trap layer according to example embodiments, a blocking film on the charge trap layer, and a gate electrode on the blocking film.

Al-doped charge trap layer and non-volatile memory device including the same

In one aspect, a method of fabricating a semiconductor device is provided. The method includes forming at least one capping layer over epitaxial source/drain regions of a PMOS device, forming a stress memorization (SM) layer over the PMOS device including the at least one capping layer and over an adjacent NMOS device, and treating the SM layer formed over the NMOS and PMOS devices to induce tensile stress in a channel region of the NMOS device.

Methods of fabrication of channel-stressed semiconductor devices

Al-doped charge trap layer, non-volatile memory device and methods of fabricating the same

A phase change memory device and a method of manufacturing the phase change memory device are provided. The phase change memory device may include a switching element and a storage node connected to the switching element, wherein the storage node includes a bottom electrode and a top electrode, a phase change layer interposed between the bottom electrode and the top electrode, and a titanium-tellurium (Ti&#x2014;Te)-based diffusion barrier layer interposed between the top electrode and the phase change layer. The Ti&#x2014;Te based diffusion barrier layer may be a TiTelayer wherein x may be greater than 0 and less than 0.5.

Storage node including diffusion barrier layer, phase change memory device having the same and methods of manufacturing the same

A method for evaluating thin films comprises the steps of inputting measurement conditions, generating electron beams from an electron source to condense the electron beams to a specimen by a condenser lens, enlarging the electron beams transmitted by the specimen with imaging lenses to image an enlarged image of the specimen, acquiring elemental maps of the specimen with an element analyzer to display the acquired elemental maps, measuring a length of the elemental maps, and correcting the measurement conditions. Disclosed is an evaluating apparatus that implements the above evaluating method.

Method and apparatus for evaluating thin films

Methods of forming a magnetic memory device include oxidizing a top magnetic layer using a conductive capping pattern as a mask. An etch selectivity between an oxidized portion of the top magnetic layer and a tunnel barrier layer may be relatively high. Using the tunnel barrier layer as an etch-stop layer, the oxidized portion of the top magnetic layer is selectively removed to form a top magnetic pattern, and to expose at least a portion of opposite sidewalls of the top magnetic pattern and the tunnel barrier layer. The unoxidized portion of the top magnetic layer forms a top magnetic pattern.

Methods of forming magnetic memory devices including oxidizing and etching magnetic layers

A semiconductor device with a stack type capacitor having a lower electrode formed of an aluminum-doped metal, and a manufacturing method thereof are provided. The semiconductor device includes: a semiconductor substrate having a gate structure and an active region; an interlayer dielectric film formed on the active region; a lower electrode formed of a metal containing aluminum on the interlayer dielectric film; a dielectric layer formed on the lower electrode; an upper electrode formed on the dielectric layer; and a plug formed in the interlayer dielectric film to electrically connect the active region with the lower electrode. The method includes: forming a gate structure and an active region on a semiconductor substrate; forming an interlayer dielectric film on the resultant semiconductor substrate; forming a plug in the interlayer dielectric film to electrically connect with the active region; forming a mold oxidation layer on the plug and the interlayer dielectric film; patterning the mold oxidation layer with a predetermined pattern and forming a lower electrode of material containing aluminum on the plug; and sequentially forming a dielectric layer and an upper electrode on the lower electrode.

Capacitor, semiconductor device having the same, and method of manufacturing the semiconductor device

A standard sample for transmission electron microscopy (TEM) elemental mapping and a TEM elemental mapping method using the same are provided. The standard sample includes a substrate; a first crystalline thin film containing heavy atoms formed on the substrate; a first amorphous thin film having oxides or nitrides containing light atoms and having a thickness of 1&#x2013;5 nm or 6&#x2013;10 nm formed on the first crystalline thin film; a second crystalline thin film containing heavy atoms formed on the first amorphous thin film. The standard sample can be used to correct TEM, EDS and EELS mapping results of a multi-layered nanometer-sized thin film and to optimize mapping conditions.

Standard sample for transmission electron microscope (TEM) elemental mapping and TEM elemetal mapping method using the same

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Gyeonggi-do, South Korea

Jong-bong Park