Lam Research Corporation

Applied Materials, Inc.

Jonathan Sungehul Kim

Kyeong-Koo Chi

Hailong Zhou

Rajinder Dhindsa

Olivier Luere

Sunil Srinivasan

Gene S Lee

Ben-Li Sheu

Camelia Rusu

Shan Jiang

Akhil Mehrotra

Zhonghua Yao

Hui Sun

Sang Wook Park

Abhijit Patil

Yangchung Lee

Martin Shim

Yoojin Kim

Lin Yu

Chain Lee

Embodiments of the present disclosure provide methods and apparatus for forming a desired material layer on a substrate between, during, prior to or after a patterning process. In one embodiment, a method for forming a material layer on a substrate includes pulsing a first gas precursor onto a surface of a substrate, attaching a first element from the first gas precursor onto the surface of the substrate, maintaining a substrate temperature less than about 110 degrees Celsius, pulsing a second gas precursor onto the surface of the substrate, and attaching a second element from the second gas precursor to the first element on the surface of the substrate.

In-situ deposition process

Implementations described herein generally relate to an etching process for etching materials with high selectivity. In one implementation, a method of etching a gate material to form features in the gate material is provided. The method includes (a) exposing a cobalt mask layer to a fluorine-containing gas mixture in a first mode to form a passivation film on the cobalt mask layer. The cobalt mask layer exposes a portion of a gate material disposed on a substrate. The method further comprises (b) exposing the portion of the gate material to an etching gas mixture in a second mode to etch the portion of the gate material. The portion of the gate material is etched through openings defined in the cobalt mask layer and the portion of the gate material is etched at a greater rate than the cobalt mask layer having the passivation layer disposed thereon.

Method of enhanced selectivity of hard mask using plasma treatments

Methods for etching a bottom anti-reflective coating (BARC) and/or an anti-reflective coating (ARC) and/or a dielectric anti-reflective coating (DARC) to form high aspect ratio features using an etch process are provided. The methods described herein advantageously facilitate profile and dimension control of features with high aspect ratios through a proper sidewall and bottom management scheme during the bottom anti-reflective coating (BARC) and/or an anti-reflective coating (ARC) and/or a dielectric anti-reflective coating (DARC) open process. In one embodiment, a method for etching a dielectric anti-reflective coating (DARC) layer to form features in the DARC layer includes supplying an etching gas mixture onto a DARC layer disposed on a substrate, wherein the substrate is disposed on a substrate support pedestal assembly disposed in a processing chamber, controlling a temperature of the substrate support pedestal assembly greater than 110 degrees Celsius, and etching the DARC layer disposed on the substrate.

Methods for high temperature etching a material layer using protection coating

A method for etching a dielectric layer is provided. The dielectric layer is disposed over a substrate and below a patterned mask having a line-space pattern. The method includes (a) providing an etchant gas comprising CF4, COS, and an oxygen containing gas, (b) forming a plasma from the etchant gas, and (c) etching the dielectric layer into the line-space pattern through the mask with the plasma from the etchant gas. The gas flow rate of CF4 may have a ratio greater than 50% of a total gas flow rate of all reactive gas components. The gas flow rate of COS may be between 1% and 50%. The method reduces bowing in etching of the dielectric layer by adding COS to the etchant gas.

Profile control in dielectric etch

A method for etching a line pattern in an etch layer disposed below an antireflective coating (ARC) layer below a patterned mask is provided. The method includes opening the ARC layer, in which an ARC opening gas comprising CF3I, a fluorocarbon (including hydrofluorocarbon) containing gas, and an oxygen containing gas are provided, a plasma is formed from the ARC opening gas to open the ARC layer, and providing the ARC opening gas is stopped. Line pattern features are etched into the etch layer through the opened ARC layer.

CD bias loading control with ARC layer open

A method for reducing line width roughness (LWR) of a feature in an etch layer below a patterned photoresist mask having mask features is provided. The method includes (a) non-etching plasma pre-etch treatment of the photoresist mask, and (b) etching of a feature in the etch layer through the pre-treated photoresist mask using an etching gas. The non-etching plasma pre-etch treatment includes (a1) providing a treatment gas containing Hand COS, (a2) forming a plasma from the treatment gas, and (a3) stopping the treatment gas.

Method for reducing line width roughness with plasma pre-etch treatment on photoresist

To achieve the foregoing and in accordance with the purpose of the present invention a method for etching an etch layer disposed below an antireflective coating (ARC) layer below a patterned mask is provided. The ARC layer is opened, and features are etched into the etch layer through the patterned mask. The opening the ARC layer includes (1) providing an ARC opening gas comprising a halogen containing gas, COS, and an oxygen containing gas, (2) forming a plasma from the ARC opening gas to open the ARC layer, and (3) stopping providing the ARC opening gas to stop the plasma. The patterned mask may be a photoresist (PR) mask having a line-space pattern. COS in the ARC opening gas reduces line width roughness (LWR) of the patterned features of the etch layer.

Line width roughness control with arc layer open

Disclosed is a method for processing a two layer mask for use in fabrication of semiconductor devices whereby the critical dimension (CD) of a semiconductor device being fabricated with the mask can be controlled. After forming a carbon mask layer and a silicon containing photoresist layer on the carbon mask, a two-step process forms openings in the carbon mask layer, as required for subsequent device fabrication. The structure is placed in a plasma processing chamber, and an oxygen plasma is employed to partially etch the carbon layer. The oxygen plasma reacts with silicon in the photoresist to form a hard silicon oxide layer on the surface of the photoresist. A hydrogen plasma is then employed to complete the etch through the carbon layer with a reduced critical dimension. Damage to the silicon containing photoresist layer is kept to a minimum during the plasma etch process by limiting the low frequency RF power.

Growing community of inventors

Danville, CA, United States of America

Jonathan Sungehul Kim