Intel Corporation

Jonathan Rosch

Wei-Lun Kane Jen

Kristof Darmawikarta

Robert Alan May

Islam A Salama

Andrew James Brown

Cheng Xu

Amruthavalli Pallavi Alur

Yikang Deng

Liwei Cheng

Shawna M Liff

Sai Vadlamani

Junnan Zhao

Siddharth K Alur

Arun Chandrasekhar

Lauren Ashley Link

A device and method for providing enhanced bridge structures is disclosed. A set of conducting and insulating layers are deposited and lithographically processed. The conducting layers have uFLS routing. A bridge with uFLS contacts and die disposed on the underlying structure such that the die are connected with the uFLS contacts and uFLS routing. For core-based structures, the layers are formed after the bridge is placed on the underlying structure and the die connected to the bridge through intervening conductive layers. For coreless structures, the layers are formed over the bridge and carrier, which is removed prior to bonding the die to the bridge, and the die bonded directly to the bridge.

Device and method of very high density routing used with embedded multi-die interconnect bridge

Embodiments include a package substrate, a method of forming the package substrate, and a semiconductor package. A package substrate includes a conductive layer in a dielectric, a first trace and a first via pad of the conductive layer having a first thickness, and a second trace and a second via pad of the conductive layer having a second thickness. The second thickness of second trace and second via pad may be greater than the first thickness of the first trace and first via pad. The dielectric may include a first dielectric thickness and a second dielectric thickness, where the second dielectric thickness may be less than the first dielectric thickness. The package substrate may include a third via having a third thickness on the first via pad, and a fourth via having a fourth thickness on the second via pad, wherein the third thickness is greater than the fourth thickness.

Dual trace thickness for single layer routing

Techniques for fabricating a cored or coreless semiconductor package having one or more magnetic bilayer structures embedded therein are described. A magnetic bilayer structure includes a magnetic layer and a dielectric layer. For one technique, fabricating a cored or coreless semiconductor package includes: depositing a seed layer on a build-up layer; forming a raised pad structure and a trace on the seed layer; removing one or more uncovered portions of the seed layer to uncover top surfaces of one or more portions of the build-up layer; applying a magnetic bilayer structure on the raised pad structure, the trace, any unremoved portion of the seed layer, and the top surfaces of the one or more portions of the build-up layer, the magnetic bilayer structure comprises a magnetic layer and a dielectric layer; and forming a conductive structure on the raised pad structure. Other techniques are also described.

Magnetic bilayer structure for a cored or coreless semiconductor package

An apparatus is provided which comprises: a woven fiber layer, a first resin layer on a first surface of the woven fiber layer, a second resin layer on a second surface of the woven fiber layer, the second surface opposite the first surface, and the first and the second resin layers comprising cured resin, a third resin layer on the first resin layer, and a fourth resin layer on the second resin layer, the third and the fourth resin layers comprising an uncured resin, and wherein the fourth resin layer has a thickness greater than a thickness of the third resin layer. Other embodiments are also disclosed and claimed.

Bi-layer prepreg for reduced dielectric thickness

An electronic interconnect may include a substrate. The substrate may include a passageway in the substrate. The passageway may extend from a first surface of the substrate toward a second surface of the substrate. The passageway may be closed at an end of the passageway. The electronic interconnect may include a plated through hole socket coupled to the passageway. The electronic interconnect may include a contact. The contact may include a pin. The pin may be configured to engage with the plated through hole socket. The electronic interconnect may include a solder ball. The solder ball may be coupled to the plated through hole socket.

Plated through hole socketing coupled to a solder ball to engage with a pin

Processes for configuring a plurality of independent die packages for socketing. The packages are attached to a carrier wafer with a release film. The attached plurality of independent die packages are overmolded to provide a molded multi-die package. The molded multi-die package is planarized to expose the dies, singulated, and released from the carrier wafer. The singulated, molded multi-die packaging may be picked for further processing and placed into a socket. A plurality of molded, multi-die packages may be placed in a socket and operate as a computer system. The independent die packages may each perform and same computer application function or different computer application functions, and may have the same or different dimensions. The socket may have any of a number of configurations as may be needed.

Multi-packaging for single-socketing

A multi-layer solder-resist provides useful adhesion to a semiconductor device package substrate while allowing for increasingly small geometries of bond pads and spacings.

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Mesa, AZ, United States of America

Jonathan Rosch