Sandisk Technologies Inc.

Sandisk Corporation

Jonathan Huynh

Feng Q Pan

Jongmin Park

Qui V Nguyen

Sung-En Wang

Khin Htoo

Trung Pham

Steve Choi

Yuxin Wang

Albert Chang

Yan Li

Xiang Yang

Dana Lee

Bo Lei

Tien-Chien Kuo

Tai-Yuan Tseng

Kwang-Ho Kim

Sagar Magia

Jong Hak Yuh

Yen-Lung Li

Marco Cazzaniga

Shankar Guhados

Viswakiran Popuri

Albert I-Ming Chang

Maurice Chen

Tien Chien Kuo

Feng Pang

Khanh Nguyen

The memory device includes a memory block that has a plurality of memory cells that are arranged in a plurality of word lines and in a plurality of channels. The memory device also includes circuitry that is configured to conduct a hole pre-charge operation to inject holes into the plurality of channels. During the hole pre-charge operation, the circuitry applies a positive CELSRC pre-charge voltage to a source line of the memory block and applies a negative unselected word line pre-charge voltage to a plurality of unselected word lines in the memory block to make a plurality of memory cells in the memory block conductive to holes.

Channel pre-charge process for memory devices using hole pre-charge operation

Techniques are presented for determining current leakage from a memory array or other circuit based on a low voltage path. For example, the technique can be applied to determine word line to word line leakage. By looking at a count for the clock used in regulating the low voltage output node, the amount of leakage can be determined. The leakage determination can be performed as part of test process or during normal memory operations.

High accuracy leakage detection through low voltage biasing

Systems and methods for reducing sensing time for sensing data states stored within a plurality of memory cells are described. In some cases, the ramping of a word line connected to the plurality of memory cells may be delayed until a threshold current corresponding with a particular number of erased memory cells of the plurality of memory cells has been met or exceeded. The threshold current may be compared with a summation of a first set of detection currents corresponding with a first set of memory cells of the plurality of memory cells that have been sensed to be in a conducting state while the word line is set to a voltage level for sensing erased memory cells. The threshold current may be set based on a chip temperature and/or a particular number of bit errors that occurred during a prior sensing operation.

Fast scan to detect bit line discharge time

Techniques are presented for determining current levels based on the behavior of a charge pump system while driving a load under regulation. Rather than diving the load directly, a fixed pump output voltage is used to supply a step-down regulator, which it turn drives the load at the selected voltage. While driving the load under regulation, the number of pump clocks during a set interval is counted. This can be compared to a reference that can be obtained, for example, from the numbers of cycles needed to drive a known load current over an interval of the duration. By comparing the counts, the amount of current being drawn by the load can be determined. This technique can be applied to determining leakage from circuit elements, such as word lines in a non-volatile memory.

Charge pump based over-sampling with uniform step size for current detection

Techniques and apparatuses for identifying weak charge pumps and for setting an optimal clock period for charge pumps to minimize variations in a current-voltage characteristic. A current sink which absorbs a specified current is connected to an output node of a charge pump. In one approach, a success or fail status is set for a charge pump by driving it with a specified clock period in a constantly pumping mode and determining if the output voltage reaches a specified output voltage. In another approach, a success or fail status is set for a charge pump by driving it with a specified clock period in a regulation mode and determining if the period in which the output voltage cycles is a specified multiple, e.g., 2&#xd7;, of a period of the clock signal. In another approach, an optimal clock period is determined.

Charge pump strength calibration and screening in circuit design

A circuit for providing a plurality of clock signals of differing frequencies includes: a phase locked loop section including a first voltage controller oscillator, connected to receive a reference clock value and generate therefrom a first voltage level, wherein the first voltage controller oscillator receives the first voltage level and generates therefrom a first clock signal; and one or more second voltage controller oscillators, each connected to receive the first voltage level, a corresponding trim value and a corresponding control voltage and derive therefrom a corresponding second clock signal.

Multi-clock generation through phase locked loop (PLL) reference

In non-volatile memories, bit lines and word lines commonly to driving and decoding circuitry on a single end. Techniques are presented for determining the time constant associated with charging the far end of such lines from the near end, at which the circuitry is connected. While driving a discharged line from the near end, the number of clock cycles for the current to drop from a first level to a second level can be used to estimate the time constant for the far end. Alternately, the line can be initially charged up, after which the current is monitored at the near end. The differences in time constants for different word lines can be used to vary the time used when accessing a selected word line.

Single ended word line and bit line time constant measurement

To maintain stability of memory array operations, a supplemental current can supply a common source line of a memory array so that the combined current from the memory array and supplemental current is at least a minimum regulation current level. When enabled for sensing operations, a driver circuit maintains the common source line's voltage level. A current subtractor circuit determines the difference between a reference current and a current proportional to the current flowing from the array, where the reference current is proportional to the minimum regulation current. The difference current is then mirrored by a self-adjusting current loop and supplied to the common source line to maintain its current level.

Self-adjusting regulation current for memory array source line

A high voltage step regulator, such as would be used to provide a regulated low voltage (on the order of a few volts) from a high voltage external supply (e.g. 12V), is presented. To protect the output transistor, through which the output is provided from the input, from breakdown, a depletion type device is connected between the supply and the output transistor. The control gate of the depletion device is then connected to the output level of the regulator. This reduces the voltage drop across the output transistor, helping to avoid violating design rules (EDR) on how great a voltage differential can be placed across the output transistor. Examples of applications for such a circuit are for various operating voltages on a non-volatile memory chip operating with a high voltage power supply.

High voltage step down regulator with breakdown protection

Apparatus and methods are provided for a temperature-compensated oscillator adapted to receive an input reference current. The apparatus and methods include or provide a temperature coefficient control circuit adapted to adjust the input reference current based on temperature information, wherein the temperature coefficient control circuit receives a first signal corresponding to the temperature information at a first signal node, and a second signal corresponding to a trimmed bias signal at a second signal node.

Methods and apparatus for clock oscillator temperature coefficient trimming

In 3D NAND type memory structures, such as of the BiCS type, the NAND strings have a channel that runs vertically up from the substrate between the memory cells and select gates. In an erase process, holes travel up from the well down at the substrate up towards the bit line in order to reach the cells to be erased. In such a process, the voltage applied to source side select gates should be low enough for the holes to pass through theses gates and up the column, but not so low as to result in device breakdown as the erase voltage is applied to the well. Techniques are presented to do this by controlling the source side select gate voltages so that the difference from the well voltage is kept largely constant during the erase process by use of a fixed offset during ramping and at the final level for the erase process.

Digitally controlled source side select gate offset in 3D NAND memory erase

Techniques and corresponding circuitry are presented for controlling the amount of current flowing through the cells of a memory circuit during a sensing operation though a feedback arrangement. The amount of current supplied to bit lines from an external power supply by regulation circuitry is compared with a reference level. Based on this comparison, the level on the control gates of clamp transistors in the sense amp circuits is set to control the amount of current supplied to the bit lines. This can reduce device variation since the levels are replicated locally at the generator on the chip. The circuitry can also be used more generally to determine the current level drawn during a sensing operation.

Cell current control through power supply

To maintain stability of memory array operations, a current source supplies a common source line of a memory. The magnitude of the regulation current from the source is dynamically determined based on the amount of current from the array itself through use of a feedback control signal provided by a current comparator circuit. The current comparison circuit can use either a digital or an analog implementation.

Dynamic regulation of memory array source line

A charge pump is regulated based up its output level. The regulation circuitry adjusts the frequency of the pump's clock based on feedback from pump's output. The pump's clock signal is generated by an oscillator whose frequency depends on a reference voltage level. The reference voltage level is dependent upon a regulation signal. In an example, a transistor whose gate is controlled by the regulation level is part of a series of elements in voltage divider, where the reference value is taken from a node of the divider.

Dynamic load matching charge pump for reduced current consumption

Techniques are presented for improving the efficiency of charge pumps. A charge pump, or a stage of a charge pump, provides its output through a pass gate. For example, this could be a charge pump of a voltage doubler type, where the output is supplied through pass gate transistors whose gates are connected to receive the output of an auxiliary section, also of a voltage doubler type of design. The waveforms provided to the gates of the pass gate transistors are modified so that their low values are offset to a higher value to take into account the threshold voltage of the pass gate transistors. In a voltage doubler based example, this can be implemented by way of introducing diodes into each leg of the auxiliary section.

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San Jose, CA, United States of America

Jonathan Huynh