Rudolph Technologies, Inc.

Mks Instruments, Inc.

Yield Dynamics, Inc.

Yield Dyamics, Inc.

Jonathan B Buckheit

Weidong Wang

Tom T Ho

Xin Sun

David W Budd

A system and method for yield management are disclosed wherein a data set containing one or more prediction variable values and one or more response variable values is input into the system. The system can process the input data set to remove prediction variables with missing values and data sets with missing values based on a tiered splitting method to maximize usage of all valid data points. The processed data can then be used to generate a model that may be a decision tree. The system can accept user input to modify the generated model. Once the model is complete, one or more statistical analysis tools can be used to analyze the data and generate a list of the key yield factors for the particular data set.

Semiconductor yield management system and method

A system and method for defect analysis are disclosed wherein a defect data set is input into the system. A radius value is selected by a user, which is the maximum number of bits that bit failures can be separated from one another to be considered a bit cluster. When a defect data set is received, the system and method start with a fail bit and search for neighboring fail bits. The specified radius is used to qualify the found fail bits to be part of the bit cluster or not. If a minimum count of fail bits is not met, the system and method will stop searching and move to the next fail bit. If a minimum count of fail bits is met, the search continues for the next fail bit until the maximum fail bit count specified by the user is reached. Aggregation is provided such that once bit clusters have been classified, the number of clusters that have the exact match or partial match to each other is counted. The user may set the partial match as a threshold count to establish a match.

Bitmap cluster analysis of defects in integrated circuits

A system and method for yield management is disclosed wherein a data set containing one or more prediction variable values and one or more response values is input into the system. The system can pre-process the input data set to remove prediction variables with missing values and data sets with missing values. The pre-processed data can then be used to generate a model that may be a decision tree. The system can accept user input to modify the generated model. Once the model is complete, one or more statistical analysis tools can be used to analyze the data and generate a list of the key yield factors for the particular data set.

A system and method for defect analysis of multi-level memory cell devices and embedded multi-level memory in system-on-chip integrated circuits are disclosed wherein a defect data set is input into the system. When a defect data set is received, an automated test engineering system running a memory test program analyzes the defect data set to generate one or more fail bit locations and one or more fail states of the memory. The multi-level memory defect analysis system and method then classify failed bits or patterns comprising a vertical fail pattern, whereby after being classified, each memory cell failure vertical fail pattern has three data attributes comprising fail type, a number of fail bits/states, and a sequence of the fail states. The vertical fail pattern may comprise a single fail state or multi-state fail. The multi-state fail may be a continuous-states fail, discontinuous-states fail, or all-state fail. The multi-level memory defect analysis system and method may additionally enable classification of failed bits or patterns comprising a lateral fail pattern. The lateral fail pattern may be a gradual fail pattern, periodic fail pattern, or random fail pattern.

Analysis techniques for multi-level memory

A system and method for analyzing error information from a semiconductor fabrication process. The system receives wafer map data describing a plurality of failing chips on a particular semiconductor wafer. The system utilizes the wafer map data to classify each of the failing chips into one of several error categories, such systematic errors, repeated or reticle errors, and random errors. The system further partitions the systematic errors into spatial clusters, which may be compared against a known library of spatial error patterns for identifying the origins of the systematic errors.

Growing community of inventors

Los Altos, CA, United States of America

Jonathan B Buckheit