Freescale Semiconductor,inc.

Nxp Usa, Inc.

Nxp B.v.

Intersil Americas Inc.

Jon Scott Choy

Karthik Ramanan

Anirban Roy

Jacob Williams

Padmaraj Sanjeevarao

Michael Alan Sadd

Chen He

Richard Eguchi

Michael Garrett Neaves

David W Chrudimsky

Yanzhuo Wang

Tahmina Akhter

Maurits Mario Nicolaas Storms

Bruce L Morton

Michael Todd Berens

Nihaar N Mahatme

Kerry A Ilgenstein

Khoi Mai

Timothy J Strauss

Fernando Zampronho Neto

Fernando Chavez Porras

Gowrishankar L Chindalore

Thomas Jew

Richard Titov Lara Saez

Gilles Muller

Walter Luis Tercariol

Peter J Kuhn

Kelly K Taylor

Srinivas Jallepalli

Christopher N Hume

Richard Kenneth Glaeser

Walter Luis L Tercariol

Gilles Joseph Maurice Muller

Thomas Stephen Harp

Silvia Wagemans

Christopher Nelson Hume

Timothy Strauss

Luis Eduardo Rueda Guerrero

A non-volatile memory (NVM) includes a daisy chained normal read bus, a daisy chained verify read bus, and a plurality of partitions. Each partition includes a portion of the daisy chained normal read bus and a portion of the daisy chained verify read bus. A memory controller receives read data in response to normal read access requests to the NVM via the daisy chained normal read bus and, in response to write access requests to the NVM, receives verify read data via the daisy chained verify read bus. A bus sharing circuit is coupled between a first partition and a second partition. The bus sharing circuit, in response to a sharing control signal, selectively repurposes portions of the daisy chained verify read bus in at least one of the partitions to communicate read data to the memory controller in response to a normal read access request to the NVM.

Partitioned non-volatile memory (NVM) having a normal read bus and a verify read bus

A magnetoresistive random access memory (MRAM) array includes MRAM cells, each MRAM cell having a corresponding Magnetic Tunnel Junction (MTJ) capable of being in a blown state or non-blown state, in which the blown state corresponds to a permanent breakdown of a tunnel dielectric layer of the corresponding MTJ. Write circuitry performs a one-time-programmable (OTP) write operation to blow selected MRAM cells. For each MRAM cell being blown, the write circuitry uses an initial OTP program reference for the MRAM cell being blown to detect onset of tunnel dielectric breakdown after application of each OTP write pulse of the OTP write operation. After detection of the onset, the write circuitry updates the initial OTP program reference, applies at least one additional OTP write pulse to the MRAM cell being blown, and uses the updated OTP program reference to verify that current saturation of the MRAM cell being blown has occurred.

Memory with one-time programmable (OTP) cells

A magnetoresistive random access memory (MRAM) array includes a data array and a sensor array. Each MRAM cell includes a Magnetic Tunnel Junction (MTJ). Each MRAM cell of the data array stores a data bit. A first and second column of the sensor array are connected to form a sensor column which includes sensor cells, each formed by a first MRAM cell in the first column together with a second MRAM cell in the second column along a same word line. Only one of a first MTJ of the first MRAM cell or second MTJ of the second MRAM cell is used as an MTJ of the sensor cell, and drain electrodes of select transistors of the first and second MRAM cells are electrically connected. Read circuitry provides read data from the data array and a sensor output indicative of a rupture state of an MTJ of the sensor array.

Magnetoresistive random access memory (MRAM) with end of life margin sensor

Memory built-in self-test (MBIST) circuitry for a disruptive memory includes an address sequencer configured to select an address with the disruptive memory as a test location, and control circuitry configured to direct a test sequence including a plurality of test operations on the test location. The control circuitry includes a first fault counter and a second fault counter, in which the control circuitry is configured to, after each test operation of the test sequence, determine whether to selectively update a first fault counter and whether to selectively update a second fault counter. The address sequencer, after completion of the test sequence, selects a next address within the disruptive memory as a next test location.

Testing disruptive memories

A main memory includes a first plurality of input/outputs (I/Os) configured to output data stored in the main memory in response to a read access request. A first portion of the first plurality of IOs provides user read data in response to the read access request and a second portion of the first plurality of IOs provides candidate replacement IOs. Repair circuitry is configured to selectively replace one or more IOs of the first portion of IOs using one or more of the candidate replacement IOs of the second portion of IOs to provide repaired read data in response to the read access request in accordance with repair mapping information corresponding to an access address of the read access request. A static random access memory (SRAM) stores repair mapping information, and a repair cache stores cached repair mapping information from the SRAM for address locations of the main memory.

Column repair in a memory system using a repair cache

A memory includes read circuitry for reading values stored in memory cells. The read circuitry includes flipped voltage followers for providing bias voltages to nodes of current paths coupled to sense amplifiers during memory read operations.

Memory read circuitry with a flipped voltage follower

A memory includes a plurality of one-time programmable (OTP) memory cells, wherein each OTP memory cell includes a corresponding storage element capable of being in a permanently blown state or non-blown state. In the non-blown state, the corresponding storage element is capable of being in a low conductive state (LCS) or high conductive state (HCS). Control circuitry is configured to, in response to a received read request having a corresponding access address which selects a set of OTP memory cells, direct write circuitry to apply a voltage differential across the corresponding storage element of each selected OTP memory cell sufficient to set the corresponding storage element to a predetermined one of the LCS or HCS, and, after the write circuitry applies the voltage differential across the corresponding storage element, direct read circuitry to read the selected OTP memory cells to output read data stored in the selected OTP memory cells.

Memory with one-time programmable (OTP) cells and reading operations thereof

A non-volatile memory includes resistive cells, write circuitry, and write detect circuitry. Each resistive cell has a resistive storage element and is coupled to a corresponding first column line and corresponding second column line. The write circuitry is configured to provide a write current through a resistive storage element of a selected resistive memory cell during a write operation based on an input data value. The write detect circuitry is configured to generate a reference voltage using a voltage at the corresponding first column line coupled to the selected resistive memory cell at an initial time of the write operation, and, during the write operation, after the initial time, provide a write detect signal based on a comparison between the voltage at the corresponding first column line coupled to the selected resistive memory cell and the reference voltage, wherein the input data value is based on the write detect signal.

Non-volatile memory having write detect circuitry

A memory includes a pair of sense amplifiers where the pair of sense amplifiers perform a multiphase memory operation to read data from two memory cells. Each sense amplifier includes two current paths. During a first phase of the memory read operation, one of the two sense amplifiers provides current through both a first memory cell and a first reference cell and the other sense amplifier of the two provides current through both a second memory cell and a second reference cell. The reference cells each have different resistance values. During a second phase of the memory read operation, one of the sense amplifiers provides current through both of the first memory cell and the second reference cell and the second sense amplifier provides current through the second memory cell and the first reference cell.

Memory with sense amplifiers

A memory includes virtual ground circuitry configured to generate a virtual ground voltage (greater than zero volts) at a virtual ground node, a memory array of resistive memory cells in which each resistive memory cell includes a select transistor and a resistive storage element and is coupled to a first column line of a plurality of first column lines, and a first decoder configured to select a set of first column lines for a memory read operation from a selected set of the resistive memory cells. The memory includes read circuitry, and a first column line multiplexer configured to couple each selected first column line of the set of first column lines to the read circuitry during the memory read operation, and configured to couple each unselected first column line of the plurality of first column lines to the virtual ground node during the memory read operation.

Non-volatle memory with virtual ground voltage provided to unselected column lines during memory read operation

A memory includes memory cells having two select transistors per cell. Each of the two select transistors are coupled to two different word lines with each word line being controlled by a separate addressable word line driver circuit. In some embodiments, providing two different word lines from two different word line drivers may provide for a memory where the word lines can apply different voltages based on the memory operation being performed.

Memory with cells having multiple select transistors

A non-volatile memory includes virtual ground circuitry configured to generate a virtual ground voltage at a virtual ground node, a memory array of memory cells in which each memory cell includes a select transistor and a storage element and is coupled to a first column line of a plurality of first column lines; and a first decoder configured to select a set of first column lines for a memory write operation to a selected set of the memory cells. The non-volatile memory also includes write circuitry configured to receive a write value for storage into the selected set of memory cells, and a first column line multiplexer configured to, during the memory write operation, couple each selected first column line of the set of first column lines to the write circuitry, and couple each unselected first column line of the plurality of first column lines to the virtual ground node.

Non-volatile memory with virtual ground voltage provided to unselected column lines during memory write operation

As disclosed herein, a memory includes an array of resistive memory cells and a voltage regulator circuit that provides a regulated voltage based on a circuit with a replica resistive storage element. The regulated voltage is applied to a mux transistor of a multiplexer of a column decoder that is used to select a particular column line of a memory array from a set of column lines to provide the proper voltage to the memory cell during a write operation to the memory cell.

Non-volatile memory with multiplexer transistor regulator circuit

A memory includes a plurality of word line drivers with each driver controlling the voltage of a word line and the voltage of a select line during a memory operation. The driver operates to couple the select line to a first voltage setting terminal when the word line is asserted and couple the select line to a second voltage setting terminal when the word line is not asserted.

Memory with select line voltage control

A leakage measuring circuit includes a bias input node control circuit and provides a signal indicative of a leakage current through the bias input node. The bias input node control circuit includes a first input to receive an indication of a reference voltage, a second input to receive an indication of a voltage of the bias input node, and an output to bias the bias input node at the reference voltage based on a relationship between the first and second input. A well voltage bias circuit provides a well bias voltage and includes a well bias control circuit including a first input to receive the signal indicative of the leakage current, a second input to receive a signal indicative of a reference leakage current value, and an output for controlling the well bias voltage based on a relationship between the first and second input of the well bias control circuit.

Growing community of inventors

Austin, TX, United States of America

Jon Scott Choy