Texas Instruments Corporation

Jon Lescrenier

Wah Kit Loh

Xiaowei Deng

Kemal Tamer San

Beena Pious

Md Abul Bashar Khan

An integrated circuit containing a memory and a sense amplifier. The integrated circuit also containing an extended delay circuit which extends the delay between when a precharged bitline is floated and when a wordline is enabled. A method of testing an integrated circuit to identify bitlines with excessive leakage.

Bitline leakage detection in memories

A method () for determining various bit failure modes in a static random access memory device. A hard/soft bit failure test sequence is performed on each cell of the memory device to determine whether the cell exhibits a hard bit failure or a soft bit failure, then a data retention test is performed on the cell having soft bit failure to determine whether the cell exhibits a data retention failure. A write or disturb test sequence is then performed on the cell not having data retention failure, and a read or disturb test sequence is performed on the cell having write or disturb failure. Finally, a disturb test sequence is performed on the cell having read or disturb failure, and then an analysis is performed on the data from the tests to determine whether the cell exhibits one of a write, read, or disturb failure.

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Jon Lescrenier