International Business Machines Corporation

Johnny James LeBlanc

Timothy Michael Skergan

Ravi Kumar Arimilli

Donald George Mikan, Jr

Samuel I Ward

Salim Ahmed Shah

Dale A Rickard

John Stanley Bialas, Jr

Daniel L Stanley

Visweswara Rao Kodali

Ronald Gene Walther

Talal K Jaber

Roger Ned Bailey

Joseph W Yoder

Timothy B Brodnax

Steven A King

Thomas M Storey

Kevin William McCauley

Daniel W Cervantes

Patrick R Crosby

Clark J Spencer

Henry C Baron

A method for test pattern compression generates a first test pattern comprising a plurality of bits. The method identifies bits comprising a don't-care bit value in the first test pattern and replaces the identified bit values with random bit values, to generate a second test pattern. The method determines a fault coverage level of the second test pattern. In the event the determined fault coverage level of the second test pattern exceeds a predetermined individual test pattern fault coverage level, for at least one bit position in the second test pattern corresponding to a replaced identified bit value and detecting at least one fault, the method exchanges the don't care value in the bit position in the first test pattern with the bit value in the corresponding bit position in the second test pattern. The method merges subsequent test patterns that increase fault coverage with the second test pattern.

Test pattern compression

A method and apparatus for testing path delays in a high-speed boundary scan implementation overcomes limitations imposed by pipelined high-speed clocking architectures used in integrated circuits. A special phase hold circuit provides a mechanism for clocking circuits undergoing dynamic tests, permitting the dynamic test to produce proper results when the integrated circuit under test is clocked with a high-speed distributed clock. The functional logic clock enable is pipelined to synchronize the functional mode clock with the test mode clock when the tester mode is switched.

Method and apparatus for testing path delays in a high-speed boundary scan implementation

A method and system for testing an integrated circuit (IC) comprising a plurality of logic units and a plurality of level sensitive scan design latches (LSSD) chains (scan chains) where the partitioning of the scan chains is different than the partitioning of the logic units. Scan blocks, each scan block comprising multiplexers, a pseudo random pattern generator (PRPG), a partitioned multiple input shift register (MISR), functional logic and control function logic are distributively placed around and close to scan inputs and scan outputs of the IC in otherwise unused area too small for larger functional logic blocks. The MISR, which contains many loaded latches and other logic, would normally be the largest element of the scan block has been partitioned into a sub-set of a full MISR to minimize the size of an individual scan block. The scan block has the functionality to enable LSSD testing, system testing and logic built in self test (LBIST) by the way the individual scan blocks are wired to the scan inputs and scan outputs of the logic units within the IC. Two or more scan blocks are needed to make a complete MISR depending on the sub-set partitioning of the MISR in each scan block. Scan block may have particular IC scan inputs and scan outputs wired into many different multiplexer inputs maintaining a known testability so wiring at the local level may be optimized. Since most of the wiring to the logic unit scan chains, wiring to the central scan switch is minimized reducing wiring complexity and cost. By partitioning the MISR, the size of the standardized Scan blocks is minimized allowing the most effective placement around logic units.

Globally distributed scan blocks

A method and apparatus for pipelining clock control signals across a chip. The present invention avoids the need for multiple clock distribution systems by allowing clock controls for clock stopping, scanning, and debugging to be distributed to all local clock buffers through pipelined non-scan latches. The test control pipeline latches may be routed along with the clock through the clock receiver, the central clock buffer, and the sector buffer areas of the chip. A relatively low speed testing mechanism may be used to drive the testing of the chip externally. The test clock is synchronized with a free-running clock on the chip to allow the circuit to be operated at speed during the testing of the chip. During boundary scan, the pipelined controls are forced to static levels which are active levels for scanning. Non-pipelined signals control the boundary scan operation based directly on the TCK clock defined in the IEEE 1149.1 boundary scan standard.

Method and apparatus for implementing IEEE 1149.1 compliant boundary scan

A method and apparatus for pipelining clock control signals across a chip. The present invention avoids the need for multiple clock distribution systems by allowing clock controls for clock stopping, scanning, and debugging to be distributed to all local clock buffers through pipelined non-scan latches. The test control pipeline latches may be routed along with the clock through the clock receiver, the central clock buffer, and the sector buffer areas of the chip. A relatively low speed testing mechanism may be used to drive the testing of the chip externally. The test clock control signals are synchronized with a free-running clock on the chip to allow the circuit to be operated at speed during the testing of the chip.

Method and apparatus for scanning and clocking chips with a high-speed free running clock in a manufacturing test environment

A method and implementing system is provided in which input signal specifications, element internal delays and output loads, for each element in a circuit design, are utilized in an iterative processing engine to objectively determine and provide a timing rule database for a circuit being designed. A schematic database netlist is run through a test model converter program to provide a test model database at a gate level for the test model design circuit. These data are processed by a designer through a workstation GUI and the result is applied to an I/O design testing function. The results of the I/O design testing function include a listing of patterns of input combinations which are needed to get listed outputs. The GUI prepares a sequence of stimuli to test the circuit with a timing simulator. Based on the output response of the timing simulator, delay relationships under various input and output load conditions are compiled.

Analyzing CMOS circuit delay

A latch circuit (,) includes a feedback path which is isolated from a circuit critical path (,). A scan input component (,) is coupled to the feedback path for providing scan test data to the latch circuit (,). A scan output component (,) may also be coupled to the feedback path for providing a separate scan out signal.

Scanable latch circuit and method for providing a scan output from a latch circuit

A system for testing a high speed integrated circuit includes a test device having a test clock with a first maximum frequency for performing level sensitive scan design (LSSD) testing of the integrated circuit device under test, a frequency multiplier circuit for multiplying the test clock signal to a higher second frequency capable of operating the device under test, and a finite state machine for generating a first internal clock for testing the device under test. In a practical embodiment, the internal clock speed may be running at a frequency many multiples of the test clock. Alternatively, a method of testing a device under test (DUT) at design speed includes running a predetermined group of tests with a test device operating at a lower speed than the design speed; incorporating LSSD or boundary scan test techniques in the device under test, together with a frequency multiplying device; generating a global clock for the device under test from the frequency multiplying circuit and using a finite state machine as a synchronizer and pulse generator to control a capture clock with respect to the global clock.

Apparatus and method for testing high speed components using low speed

A method and system for performing non-standard insitu burn-in testings is disclosed. In accordance with the method and system of the present invention, a transition counter is provided for each of the integrated-circuit (IC) devices under test. A set of scan strings is transmitted to the transition counter in each of the IC devices while the IC devices are operating under a high-temperature /high-voltage environment. A determination is then made as to whether or not a value from the transition counter in each of the IC devices operating under the high-temperature environment is within a predefined range in response to the transmitted scan strings. An indicator associated with each of the IC devices operating under the high-temperature/high-voltage environment is set in response to the transition counter value that occurred outside the predefined range. The IC devices that do not have the indicator set are subsequently tested again with the IC devices operating in room temperature and nominal voltage. Each IC device that passes the second test will be accepted.

Method and system for performing non-standard insitu burn-in testings

A fault-tolerant computer system having shadow registers for storing the contents of a primary array into a shadow array at the completion of a stored instruction execution. This is accomplished in one clock cycle with all registers being shadowed simultaneously. During rollback of execution steps for a checkpoint retry, the shadow register files provide a signal cycle unload of the shadow array into the primary array. LSSD latches are used in the shadow register file.

Shadow register file for instruction rollback

The improved register file includes an array of storage cells arranged in columns and rows, each column having a pair of bit lines for writing into the cell. Each storage cell includes a flip-flop cell having a first storage node connected to a respective read line which is unique for that cell. A read address latch has an enabling input connected to the master clock signal which is the same master clock signal for the LSSD logic on the integrated circuit chip. The read address latch applies its decoded output to a multiplexer which selects those read lines coming from one of the rows of storage cells in the array, and applies those selected read lines to an output storage cell array. The output storage cell array is enabled by a slave clock signal which is the same slave clock signal employed in the LSSD logic on the same integrated circuit chip. The output storage cell array stores the data from the selected read lines out of the multiplexer. The multiplexer propagates the data signals output from the read lines and performs the selection during the delay period between the master clock signal and the slave clock signal. Thus, the circuit makes use of the dead time between the master clock signal and the slave clock signal which was heretofore wasted, in performing the selection of the read lines for latching in the output storage cell array. The feature of connecting separate read lines to each respective storage cell in the array allows the independent accessing of different register rows in the register file for reading and writing, during the same logic cycle defined by the interval for the occurrence of both the master and the slave clock pulses.

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Austin, TX, United States of America

Johnny James LeBlanc