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Infineon Technologies Ag

Siemens Aktiengesellschaft

Infineon Technologies North America Corp.

Johnathan E Faltermeier

Kangguo Cheng

Bruce Bennett Doris

Veeraraghavan S Basker

Rajarao Jammy

Ali Khakifirooz

Tenko Yamashita

Ramachandra Divakaruni

Takashi Ando

Paul Christian Parries

David M Dobuzinsky

Xuefeng Hua

Theodorus E Standaert

Oleg Gluschenkov

Sivananda K Kanakasabapathy

Herbert Lei Ho

Ulrike Gruening

Rama Divakaruni

Xi Li

Philip L Flaitz

Michael Maldei

Ruilong Xie

Lawrence Alfred Clevenger

Jack Allan Mandelman

Toshiharu Furukawa

Hemanth Jagannathan

Xiuyu Cai

Injo Ok

Su Chen Fan

Helmut Horst Tews

Byeong Yeol Kim

Devendra K Sadana

Edward J Nowak

Stephen W Bedell

Judson Robert Holt

Reinaldo Ariel Vega

Kern Rim

Kevin Shawn Petrarca

Ravikumar Ramachandran

Huiming Bu

Yun-Yu Wang

Emre Alptekin

Chun-Chen Yeh

Jochen C Beintner

Viraj Yashawant Sardesai

Kaushik Arun Kumar

Larry Alan Nesbit

Stephan Grunow

Christopher Carr Parks

Chienfan Yu

Mahender Kumar

Munir D Naeem

Suryanarayan G Hegde

Mihel Seitz

Paul Andrew Ronsheim

Michael D Steigerwalt

Radhika Srinivasan

Irene Lennox McStay

Brian S Lee

Carol J Heenan

Brent A Anderson

Carl John Radens

William R Tonti

Yun Yu Wang

Shom Ponoth

Ying Di Zhang

Ryota Katsumata

Geng Wang

Michael Patrick Chudzik

Subramanian Srikanteswara Iyer

Laertis Economikos

Rolf Weis

John Edward Barth, Jr

Babar Ali Khan

Wayne Frederick Ellis

Tze-Chiang Chen

Randy William Mann

Keitaro Imai

Kwong Hon Wong

Xinhui Wang

Vidhya Ramachandran

Hiroyuki Akatsu

Stephan Kudelka

Hyun-Jin Cho

Joseph Francis Shepard, Jr

William J Cote

Jay William Strane

Wolfgang Bergner

David R Hanson

Byeongju Park

Deok-kee Kim

Rajesh Rengarajan

Jeremy K Stephens

Kenneth T Settlemyer, Jr

Kam-Leung Lee

Balasubramanian S Pranatharthi Haran

Matthias Ilg

Larry Clevenger

James Patrick Norum

Nathaniel C Berliner

A method of forming a semiconductor structure includes depositing a gate dielectric layer lining a recess of a gate structure formed on a substrate with a first portion of the gate dielectric layer covering sidewalls of the recess and a second portion of the gate dielectric layer covering a bottom of the recess. A protective layer is deposited above the gate dielectric layer and then recessed selectively to the gate dielectric layer so that a top surface of the protective layer is below of the recess. The first portion of the gate dielectric layer is recessed until a top of the first portion of the gate dielectric layer is approximately coplanar with the top surface of the protective layer. The protective layer is removed and a conductive barrier is deposited above the recessed first portion of the gate dielectric layer to cut a diffusion path to the gate dielectric layer.

Replacement metal gate stack for diffusion prevention

A gate structure straddling a plurality of semiconductor material portions is formed. Source regions and drain regions are formed in the plurality of semiconductor material portions, and a gate spacer laterally surrounding the gate structure is formed. Epitaxial active regions are formed from the source and drain regions by a selective epitaxy process. The assembly of the gate structure and the gate spacer is cut into multiple portions employing a cut mask and an etch to form multiple gate assemblies. Each gate assembly includes a gate structure portion and two disjoined gate spacer portions laterally spaced by the gate structure portion. Portions of the epitaxial active regions can be removed from around sidewalls of the gate spacers to prevent electrical shorts among the epitaxial active regions. A dielectric spacer or a dielectric liner may be employed to limit areas in which metal semiconductor alloys are formed.

Gate structure cut after formation of epitaxial active regions

A semiconductor structure includes a semiconductor substrate having an outer surface; a plurality of oxide regions, located outward of the outer surface, and defining a plurality of metal-gate-stack-receiving cavities; and a liner interspersed between the plurality of oxide regions and the semiconductor substrate and between the plurality of oxide regions and the plurality of metal-gate-stack-receiving cavities. A layer of high-K material is deposited over the semiconductor structure, including on outer surfaces of the plurality of oxide regions, outer edges of the liner, on walls of the plurality of metal-gate-stack-receiving cavities, and on the outer surface of the semiconductor substrate within the plurality of metal-gate-stack-receiving cavities. The layer of high-K material is chamfered to remove same from the outer surfaces of the plurality of oxide regions, the outer edges of the liner, and partially down the walls of the plurality of metal-gate-stack-receiving cavities.

High-K layer chamfering to prevent oxygen ingress in replacement metal gate (RMG) process

One embodiment provides a method comprising etching a fin of a fin-shaped field effect transistor (FinFET) to form a reduced fin, and laterally etching the reduced fin to form a fin channel including a first fin channel sidewall and a second fin channel sidewall opposing the first fin channel sidewall. The method further comprises forming a first thin dielectric tunnel and a second thin dielectric tunnel on the first fin channel sidewall and the second fin channel sidewall, respectively. Each thin dielectric tunnel prevents lateral epitaxial crystal growth on the fin channel. The method further comprises etching an insulator layer disposed between the fin channel and a substrate of the FinFET to expose portions of a substrate surface of the substrate. A source epitaxy and a drain epitaxy are formed from vertical epitaxial crystal growth on the exposed portions of the substrate surface after epitaxial deposition.

Partially dielectric isolated fin-shaped field effect transistor (FinFET)

A method of reducing a migration of oxygen into a high-k dielectric layer of a semiconducting device is disclosed. An oxide layer of the semiconducting device is deposited on a substrate. A chemical composition of a top portion of the oxide layer is altered. The high-k dielectric layer is deposited on the top portion of the oxide layer to form the semiconducting device. The altered chemical composition of the top portion of the oxide layer reduces migration of oxygen into the high-k dielectric layer.

Nitridation on HDP oxide before high-k deposition to prevent oxygen ingress

A FinFET having spacers with a substantially uniform profile along the length of a gate stack which covers a portion of a fin of semiconductor material formed on a substrate is provided by depositing spacer material conformally on both the fins and gate stack and performing an angled ion impurity implant approximately parallel to the gate stack to selectively cause damage to only spacer material deposited on the fin. Due to the damage caused by the angled implant, the spacer material on the fins can be etched with high selectivity to the spacer material on the gate stack.

FinFET spacer formation by oriented implantation

A semiconductor substrate including a field effect transistor (FET) and a method of producing the same wherein a stressor is provided in a recess before the source/drain region is formed. The device has an increased carrier mobility in the channel region adjacent to the gate electrode.

Method for improving device performance using epitaxially grown silicon carbon (SiC) or silicon-germanium (SiGe)

Embodiments for the present invention provide a semiconductor device and methods for fabrication. In an embodiment of the present invention, a semiconductor structure comprises a first conductor horizontally formed on a semiconductor substrate. A second conductor is vertically formed in a semiconductor stack that includes the semiconductor substrate. An oxidized region is formed proximate to the first conductor. The second conductor is formed in a manner to be in electrical communication with the first conductor. The first conductor is formed in a manner to be laterally connected to the second conductor. The first conductor is formed in a manner to not traverse beneath the oxidized region. The first conductor is formed in a manner to have a reduced link-up resistance with adjacent epitaxial material included in the semiconductor structure.

Semiconductor structure having buried conductive elements

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Delanson, NY, United States of America

Johnathan E Faltermeier