Globalfoundries U.S. Inc.

Globalfoundries Singapore Pte. Ltd.

Johnatan A Kantarovsky

Siva P Adusumilli

Vibhor Jain

Jeonghyun Hwang

Mark Levy

Yves T Ngu

Michael Joseph Zierak

Ephrem G Gebreselasie

Anthony K Stamper

Sebastian Theodore Ventrone

Steven J Bentley

Rajendran Krishnasamy

Ajay Raman

John J Ellis-Monaghan

Santosh Sharma

Brett T Cucci

Henry L Aldridge, Jr

Steven M Shank

Zhong-Xiang He

Sunil Kumar Singh

Ramsey M Hazbun

Uzma B Rana

Francois Hebert

Alain F Loiseau

Michel J Abou-Khalil

Sen Liu

Uppili S Raghunathan

Richard J Rassel

Mark David Levy

Claire E Kardos

Kristin Marie Welch

Lawrence Selvaraj Susai

Yves Ngu

Embodiments of the disclosure provide an electrically programmable fuse (efuse) over crystalline semiconductor material. A structure according to the disclosure includes a plurality of crystalline semiconductor layers. Each crystalline semiconductor layer includes a compound material. A metallic layer is on the plurality of crystalline semiconductor layers. The metallic layer has a lower resistivity than an uppermost layer of the plurality of crystalline semiconductor layers. A pair of gate conductors is on respective portions of the metallic layer. The metallic layer defines an electrically programmable fuse (efuse) link between the gate conductors.

Electrically programmable fuse over crystalline semiconductor materials

A structure includes a negative temperature coefficient (NTC) resistor for use in gallium nitride (GaN) technology. The NTC resistor includes a p-type doped GaN (pGaN) layer, and a gallium nitride (GaN) heterojunction structure under the pGaN layer. The GaN heterojunction structure includes a barrier layer and a channel layer. An isolation region extends across an interface of the barrier layer and the channel layer, and a first metal electrode is on the pGaN layer spaced from a second metal electrode on the pGaN layer. The NTC resistor can be used as a temperature compensated reference in a structure providing a temperature detection circuit. The temperature detection circuit includes an enhancement mode HEMT sharing parts with the NTC resistor and includes temperature independent current sources including depletion mode HEMTs.

Temperature detection using negative temperature coefficient resistor in GaN setting

A semiconductor device is provided. The semiconductor device includes a substrate, a semiconductor layer, a device layer, and heat dissipating structures. The semiconductor layer is over the substrate and the device layer is over the semiconductor layer. The device layer includes a first ohmic contact and a second ohmic contact. The heat dissipating structures are at least through the substrate and the semiconductor layer, and between the first ohmic contact and the second ohmic contact.

High-mobility-electron transistors having heat dissipating structures

The present disclosure relates generally to structures in semiconductor devices and methods of forming the same. More particularly, the present disclosure relates to high electron mobility transistor (HEMT) devices having a silicided polysilicon layer. The present disclosure may provide an active region above a substrate, source and drain electrodes in contact with the active region, a gate above the active region, the gate being laterally between the source and drain electrodes, a polysilicon layer above the substrate, and a silicide layer on the polysilicon layer. The active region includes at least two material layers with different band gaps. The polysilicon layer may be configured as an electronic fuse, a resistor, or a diode.

High electron mobility transistor devices having a silicided polysilicon layer

A transistor structure is provided, the transistor structure comprising a source, a drain, and a gate between the source and the drain. The gate may have a top surface. A first field plate may be between the source and the drain. The first field plate may be L-shaped and having a vertical portion over a horizontal portion. A top surface of the vertical portion of the first field plate may be at least as high as the top surface of the gate. A second field plate, whereby the second field plate may be connected to the gate and the second field plate may partially overlap the horizontal portion of the first field plate.

Field effect transistors with dual field plates

The present disclosure relates to semiconductor structures and, more particularly, to multi-channel transistors and methods of manufacture. The structure includes: a gate structure; a single channel layer in a channel region under the gate structure; a drift region adjacent to the gate structure; and multiple channel layers in the drift region coupled to the single channel layer under the gate structure.

Multi-channel transistor

An integrated circuit (IC) having a high voltage semiconductor device with a plurality of field plates between the gate and drain. The IC further includes a biasing circuit electrically coupled to each of the plurality of field plates, the biasing circuit including a plurality of high voltage depletion mode transistors, each having a pinch off voltage. The high voltage depletion mode transistors may have different pinch off voltages, and each of the field plates are each independently biased by a different one of the high voltage depletion mode transistors.

High voltage device with linearizing field plate configuration

Structures with an isolation region and fabrication methods for a structure having an isolation region. The structure includes a semiconductor substrate, a first isolation region surrounding a portion of the semiconductor substrate, a device in the portion of the semiconductor substrate, and a second isolation region surrounding the first isolation region and the portion of the semiconductor substrate.

Isolation regions for charge collection and removal

Disclosed are a structure with a multi-level field plate and a method of forming the structure. The field plate includes multiple first conductors on a dielectric layer and separated from each other by spaces with different widths (e.g., by with progressively decreasing widths). A conformal additional dielectric layer extends over the first conductors and onto the dielectric layer within the spaces. The field plate also includes, on the additional dielectric layer, second conductor(s) with portions thereof extending into the spaces. Within the spaces, the second conductor portions are at different heights (e.g., at progressively increasing heights) above the dielectric layer. Such a field plate can be incorporated into a transistor (e.g., a high electron mobility transistor (HEMT)) to, not only reduce the peak of an electric field exhibited proximal to a gate terminal, but to ensure the electric field is essentially uniform level between the gate and drain terminals.

Structure including multi-level field plate and method of forming the structure

Disclosed are a transistor and a method for forming the transistor. The method includes concurrently forming gate and source/drain openings through an uppermost layer (i.e., a dielectric layer) in a stack of layers. The method can further include: depositing and patterning gate conductor material so that a first gate section is in the gate opening and a second gate section is above the gate opening and so that the source/drain openings are exposed; extending the depth of the source/drain openings; and depositing and patterning source/drain conductor material so that a first source/drain section is in each source/drain opening and a second source/drain section is above each source/drain opening. Alternatively, the method can include: forming a plug in the gate opening and sidewall spacers in the source/drain openings; extending the depth of source/drain openings; depositing and patterning the source/drain conductor material; and subsequently depositing and patterning the gate conductor material.

Transistor with multi-level self-aligned gate and source/drain terminals and methods

The present disclosure relates to semiconductor structures and, more particularly, to airgap structures in a doped region under one or more transistors and methods of manufacture. The structure includes: a semiconductor material comprising a doped region; one or more sealed airgap structures breaking up the doped region of the semiconductor material; and a field effect transistor over the one or more sealed airgap structures and the semiconductor material.

Airgap structures in auto-doped region under one or more transistors

Disclosed are embodiments of a transistor (e.g., a III-V high electron mobility transistor (HEMT), a III-V metal-insulator-semiconductor HEMT (MISHEMT), or the like) that has multiple self-aligned terminals. The self-aligned terminals include a self-aligned gate, a self-aligned source terminal and, optionally, a self-aligned drain terminal. By forming self-aligned terminals during processing, the separation distances between the terminals (e.g., between the gate and source terminal and, optionally, between the gate and drain terminal) can be reduced in order to reduce device size and to improve performance (e.g., to reduce on resistance and increase switching speeds). Also disclosed herein are method embodiments for forming such a transistor.

Transistor with self-aligned gate and self-aligned source/drain terminal(s) and methods

The disclosure provides an integrated circuit (IC) structure with fluorescent materials, and related methods. An IC structure according to the disclosure may include a layer of fluorescent material on an IC component. The layer of fluorescent material defines a portion of an identification marker for the IC structure.

Growing community of inventors

South Burlington, VT, United States of America

Johnatan A Kantarovsky