Prolinx Labs Corporation

John Y Xie

Steve S Chiang

James J Lan

William H Shepherd

Hang Jiang

An integrated circuit (IC) package substrate has a dielectric layer and a micro filled via formed substantially in the center of a hole in the dielectric layer. The IC package substrate has at least one chip bonding pad and one ball attach pad that are electrically coupled to each other by the micro filled via. The micro filled via is formed of a material called a 'micro filled via material' that includes a binding material and optionally includes a number of particles (between 0%-90% by volume) dispersed in the binding material. The binding material can be any material, such as a polymer that is either conductive or nonconductive. The particles can be formed of any conductive material, such as a conductive polymer or a conductive metal (e.g. copper or gold). An electrical conductor can be originally formed simply by contact between conductive particles located adjacent to each other. In an optional step, the micro filled via is subjected to a programming current (in a step called 'programming') to lower the resistance of an originally formed electrical conductor, or to originally form an electrical conductor by break down of a dielectric material. The IC package substrate can be formed in either a cavity up or a cavity down configuration.

Ball grid array structure and method for packaging an integrated circuit

A structure includes a support layer formed of a conductive material, such as a sheet of copper. The support layer has a number of conductive islands isolated from other portions of the support layer by isolation gaps. The support layer is sandwiched between two compound layers each of which is formed of a dielectric layer having a number of via holes and conductive elements located in the via holes. The conductive elements are formed at predetermined locations such that a conductive element in each compound layer contacts a conductive island in the support layer. The structure also includes two conductive layers formed on the two respective compound layers such that a trace in a first conductive layer is coupled to a trace in a second conductive layer through two conductive elements in the respective two compound layers and an island in the support layer. Such a structure can be formed by a number of processes. For example, the support layer can be formed by etching a sheet of conductive material, the compound layers can be formed by placing a conductive paste in via holes in a dielectric layer, and the conductive layers can be formed by lamination followed by etching to form traces.

Method for supporting one or more electronic components

A micro filled material includes a binding material and optionally includes a number of particles. The binding material and the particles can be formed of any conductive or nonconductive material. Using such a micro filled via material, an electrical conductor is formed in a substrate for supporting one or more electronic components using the following steps: placing the micro filled via material between two conductive layers at various locations in a substrate at which an electrical conductor is to be formed; and optionally programming the micro filled via material to reduce the resistance of, or to form an electrical conductor.

Method and structure to interconnect traces of two conductive layers in

Multilayer board having insulating isolation rings

A novel antifuse includes a composite of conductive particles dispersed throughout a nonconductive matrix, which composite is located inside an antifuse via. The antifuse via is defined by a dielectric layer that separates two electrodes. The electrodes can be located in the same conductive layer plane (typically parallel to and isolated from one another) or in two different conductive planes (typically formed transverse to one another and separated by a dielectric with an antifuse via formed therein). The electrodes can be coupled to, for example, active or passive regions of the integrated circuit. One embodiment of an antifuse (also called 'composite antifuse') has only the composite in an antifuse via between the two conductive layers. Another embodiment of an antifuse (also called 'hybrid antifuse') includes in addition to the composite, one or more thin dielectric layers also located in the antifuse via between the two conductive layers.

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San Jose, CA, United States of America

John Y Xie