Chrysalis Symbolic Design, Inc.

Synopsys, Inc.

John W Hagerman

Richard J Cloutier

Matthew J Bellantoni

Eyal Odiz

Lisa R McIlwain

Gerard Memmi

Kshama Jambhekar

Michael S Quayle

Phillip W Baraona

Richard J Newton, Ii

Patrick Groeneveld

Techniques and systems for concurrent formal verification of logic synthesis are described. A synthesis tool can write intermediate checkpoint designs that embody the state of an integrated circuit (IC) design under synthesis as optimization progresses. Meanwhile, formal equivalence checking proceeds in parallel with synthesis and checks the intermediate checkpoint designs for equivalence.

Concurrent formal verification of logic synthesis

A hierarchical structure for a non-hierarchical, non-ordered second representation of a circuit design is generated from a first hierarchical representation and a set of generation rules. Subsequently, the newly generated hierarchical structure is populated by design components to provide a second hierarchical representation. This second hierarchical representation enables comparison between the reference hierarchical structure and the new hierarchy representation to determine equivalence of the circuit designs associated with the new generated and reference hierarchical structure.

Rule based hierarchy generation in a circuit design verification system

A design verification system verifies whether first and second representations of a circuit design match. The system includes a processor assembly and a memory that stores a first hierarchy of elements as the first representation of the design, a second hierarchy of elements as the second representation of the design, and a map entry that identifies a correspondence between an element of the first hierarchy and an element of the second hierarchy. The processor assembly performs a read operation that reads the map entry from the memory; a generate operation that generates other map entries according to the read map entry, the generated other map entries identifying other correspondences between the elements of the first hierarchy and the elements of the second hierarchy; a store operation that stores the generated other map entries in the memory such that the map entry and the generated other map entries form a set of map entries stored in the memory; and a compare operation that compares the first representation with the second representation according to the set of map entries. The result of a comparison between the first and second representations indicates whether the first representation matches with the second representation.

Computers systems and methods for verifying representations of a circuit design

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Boxford, MA, United States of America

John W Hagerman