International Business Machines Corporation

Endicott Interconnect Technologies, Inc.

Endicott International Technologies, Inc.

John Steven Kresge

James Robert Wilcox

David Brian Stone

David Noel Light

Francis Joseph Downes, Jr

James Warren Wilson

Timothy Eugene Antesberger

Howard L Heck

Voya Rista Markovich

John M Lauffer

Robert Maynard Japp

Gerald Walter Jones

Robert David Sebesta

Scott Preston Moore

Frank Daniel Egitto

Natalie Barbara Feilchenfeld

John Joseph Konrad

Charles Robert Davis

Ajit Kumar Trivedi

Timothy Leroy Wells

Thomas P Duffy

James W Fuller, Jr

Ronald P Nowak

Stephen Krasniak

Steven L Hanakovic

John T Kolias

David John Russell

Donald Seton Farquhar

Kostas I Papathomas

Luis Jesus Matienzo

David James Alcoe

Elizabeth F Foster

Robin A Susko

Thurston Bryce Youngs, Jr

Ronald A Kaschak

Daniel C Van Hart

Sylvia Adae-Amoakoh

Cheryl L Tytran-Palomaki

Gerald G Advocate, Jr

Wayne John Howell

Eric A Johnson

Bernd Karl Appelt

Thomas P Gall

Tien Y Wu

Cheryl L Palomaki

A method of making a circuitized substrate which involves forming a plurality of individual film resistors having approximate resistance values as part of at least one circuit of the substrate, measuring the resistance of a representative (sample) resistor to define its resistance, utilizing these measurements to determine the corresponding precise width of other, remaining film resistors located in a defined proximity relative to the representative resistor such that these remaining film resistors will include a defined resistance value, and then selectively isolating defined portions of the resistive material of these remaining film resistors while simultaneously defining the precise width of the resistive material in order that these film resistors will possess the defined resistance.

Method of making circuitized substrates having film resistors as part thereof

A power core adapted for use as part of a circuitized substrate, e.g., a PCB or LCC. The core includes a first layer of low expansion dielectric and two added layers of a different low expansion dielectric bonded thereto, with two conductive layers positioned on the two added low expansion dielectric layers. At least one of the conductive layers serves as a power plane for the power core, which in turn is usable within a circuitized substrate, also provided. Methods of making the power core and circuitized substrate are also provided. The use of different low expansion dielectric materials for the power core enables the use of support enhancing fiberglass in one layer while such use is precluded in the other two dielectric layers, thus preventing CAF shorting problems in highly precisely defined thru holes formed within the power core.

Power core for use in circuitized substrate and method of making same

A method of making a circuitized substrate in which pairs of vertically oriented though holes are formed such that at least one of the through holes is partially embedded within a lower one, thus assuring a sound connection following subsequent lamination or other steps the substrate including such holes is subjected to during manufacture. An electrical assembly including a substrate with such features is also provided.

Method of making a circuitized substrate with enhanced circuitry and electrical assembly utilizing said substrate

A method of making a circuitized substrate in which the substrate's commoning bar, used during the plating of the circuitry on the substrate, is terminated from the various conductors using a laser. In a preferred embodiment, the laser acts through a dielectric layer (soldermask) which is applied over the circuitry, including the commoning bar and connected parts. The laser may also be used to expose selected ones of the circuit's other parts, including various pads used to accommodate a wirebond (from a chip) and also solder balls for eventual placement of the substrate on a larger circuit board.

Method of making circuitized substrate

A method of making a circuitized substrate in which a commoning bar, used during the plating of the circuitry on the substrate and coupled to a second set of conductors which in turn are coupled to a first set of conductors, is terminated from the second set of conductors.

A method of making an electronic package. The method includes forming a semiconductor chip and an multi-layered interconnect structure. The semiconductor chip includes a plurality of contact members on one of its surfaces that are connected to the multi-layered interconnect structure by a plurality of solder connections. The formed multi-layered interconnect structure is adapted for electrically interconnecting the semiconductor chip to a circuitized substrate (eg., circuit board) with another plurality of solder connections and includes a thermally conductive layer being comprised of a material having a selected thickness and coefficient of thermal expansion to substantially prevent failure of the solder connections between said first plurality of electrically conductive members and the semiconductor chip. The method forms the electronic package to further include a dielectric material having an effective modulus to assure sufficient compliancy of the multi-layered interconnect structure during operation.

Method of making an electronic package

A method for forming a flip-chip joinable substrate having non-plated-on contact pads. The substrate has an external metal foil layer upon a dielectric layer upon a patterned internal metal layer having an internal contact area. An area of the external metal foil layer above the internal contact area is selected. A microvia cavity extending to the internal contact area is perforated centrally within the selected area and is filled with a mass of conductive paste forming an external contact pad. The external contact pad is used as an etch mask for removing the adjacent external metal foil.

Economical high density chip carrier

A method of removing selected portions of material from a base material using a plurality of different depth cuts (e.g., using laser cutting) such that apertured sections (or segments) are expeditiously removed for eventual use with another component or otherwise. In one example, the segmented section so removed can be used to bond various elements of an electronic package which in turn can then be positioned and used within an information handling system such as a computer, server, mainframe, etc.

Material separation to form segmented product

A semiconductor chip carrier having an increased chip connector and plated through hole density. In particular, a substrate having a plurality of plated through holes therein, and a fatigue resistant redistribution layer thereon. The redistribution layer includes a plurality of vias selectively positioned over and contacting the plated through holes. The substrate further including a ground plane, two pair of signal planes, and two pair of power planes, wherein the second pair of power planes are located directly underneath the external dielectric layer. A buried plated through hole within the substrate.

Integrated circuit structure

A method for forming an electrical structure. A substrate and a compliant layer are provided. A plated through hole (PTH) is formed through the compliant layer. A top pad is formed on a top surface of the compliant layer, wherein the top pad is electrically coupled to the PTH. A bottom pad is formed on a bottom surface of the compliant layer, wherein the bottom pad is electrically coupled to the PTH. A mask layer is applied to the bottom surface of the compliant layer, wherein the mask layer covers the bottom pad and an end of the PTH. The compliant layer is joined with the substrate, mechanically and electrically at the top pad. The portion of the mask layer is removed, wherein a portion of the bottom pad is exposed.

Method for forming an electrical structure

A method of making a multi-layered interconnect structure. First and second electrically conductive members are formed on the first and second dielectric layers, respectively. The dielectric layer are formed on opposing surfaces of a thermally conductive layer. A first and second electrically conductive layer is formed within the first dielectric layer. The second electrically conductive layer includes shielded signal conductors and is positioned between the first electrically conductive layer and the thermally conductive layer. A plated through hole (PTH) formed through the interconnect structure is electrically connected to one of the first and second electrically conductive members and to one of the shielded signal conductors. A third dielectric layer, formed on the first dielectric layer and on portions of the first electrically conductive members, substantially overlies the PTH and includes a high density interconnect layer for providing an electrical path from an electronic device to the shielded signal conductors.

Method of making a multi-layered interconnect structure

A flip-chip joinable substrate having non-plated-on contact pads. The substrate has an external metal foil layer upon a dielectric layer upon a patterned internal metal layer having an internal contact area. An area of the external metal foil layer above the internal contact area is selected. A microvia cavity extending to the internal contact area is perforated centrally within the selected area and is filled with a mass of conductive paste forming an external contact pad. The external contact pad is used as an etch mask for removing the adjacent external metal foil.

An electronic structure including a metallic interlocking structure for bonding a conductive plated layer to metal surface, and a method of forming the electronic structure. The method provides a substrate having a metallic sheet within a dielectric layer. The metallic sheet includes a metal such as copper. An opening in the substrate, such as a blind via, is formed by laser drilling through the dielectric layer and partially through the metallic sheet. If the opening is a blind via, then the laser drilling is within an outer ring of the blind via cross section using a laser beam having a target diameter between about 20% and about 150% of a radius of the blind via cross section. A surface at the bottom of the opening, called a &ldquo;blind surface,&rdquo; includes a metallic protrusion formed by the laser drilling, such that the metallic protrusion is integral with a portion of the blind surface. The metallic protrusion includes the metal of the metallic sheet and at least one constituent element from the dielectric layer. The metallic protrusion is then etched to form a metallic interlocking structure that is integral with the portion of the blind surface. The metallic interlocking structure includes discrete metallic fibers, with each metallic fiber having a curved (or curled) geometry. Each metallic fiber has its own unique composition that includes the metal, at least one constituent element of the dielectric layer, or both.

Formation of a metallic interlocking structure

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Binghamton, NY, United States of America

John Steven Kresge