Advanced Micro Devices Corporation

John R Behnke

Anthony John Toprac

Matthew A Purdy

Yu Nan Sun

Hiroyuki Kinoshita

Cyrus E Tabery

Christopher Foster

Basab Banerjee

Douglas J Bonser

James H Hussey, Jr

A method for forming a semiconductor device that includes a line and space pattern with variable pitch and critical dimensions in a layer on a substrate. The substrate includes a first region (e.g., a core region) and a second region (e.g., a periphery region). A first sub-line and space pattern in the first region comprises a space of a dimension (A) less than achievable by lithographic processes alone. Further, a second sub-line and space pattern in the second region comprises at least one line including a second critical dimension (B) achievable by lithography. The method uses two critical masking steps to form a hard mask that includes in the core region a critical dimension (A) less than achievable at a resolution limit of lithography. Further, the method uses a single etch step to transfer the pattern of the hard mask to the layer.

Semiconductor device with core and periphery regions

METHOD OF FORMING CORE AND PERIPHERY GATES INCLUDING TWO CRITICAL MASKING STEPS TO FORM A HARD MASK IN A CORE REGION THAT INCLUDES A CRITICAL DIMENSION LESS THAN ACHIEVABLE AT A RESOLUTION LIMIT OF LITHOGRAPHY

A method for controlling spacer width in a semiconductor device is provided. A substrate having a gate formed thereon is provided. An insulative layer is formed over at least a portion of the substrate. The insulative layer covers the gate. The thickness of the insulative layer is measured. A portion of the insulative layer to be removed is determined based on the measured thickness of the insulative layer. The portion of the insulative layer is removed to define a spacer on the gate. A processing line for forming a spacer on a gate disposed on a substrate includes a deposition tool, a thickness metrology tool, and automatic process controller, and a spacer etch tool. The deposition tool is adapted to form an insulative layer over at least a portion of the substrate. The insulative layer covers the gate. The thickness metrology tool is adapted to measure the thickness of the insulative layer. The automatic process controller is adapted to determine a portion of the insulative layer to be removed based on the measured thickness of the insulative layer. The spacer etch tool is adapted to remove the portion of the insulative layer to define a spacer on the gate.

System for controlling transistor spacer width

The present invention provides for a method and an apparatus for controlling critical dimensions. At least one run of semiconductor devices is processed. A critical dimension measurement is performed upon at least one of the processed semiconductor device. An analysis of the critical dimension measurement is performed. A secondary process upon the semiconductor device in response to the critical dimension analysis is performed.

Method and apparatus for control of critical dimension using feedback etch control

Method for controlling transistor spacer width

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Austin, TX, United States of America

John R Behnke