International Business Machines Corporation

John R Abernathey

Jerome Brett Lasky

Randy William Mann

Paul Christian Parries

Scott R Stiffler

Julie Anne Springer

John Edward Cronin

Charles W Koburger, Iii

Timothy Harrison Daubenspeck

Pai-Hung Pan

Stephen Ellinwood Luce

Larry Alan Nesbit

Rosemary A Previti-Kelly

David L Johnson

Jung H Yoon

Thomas O Sedgwick

Wayne I Kinney

Gary P Viens

Denis J Poley

Charles A Paquette

A method of forming interconnections of devices of integrated circuits, especially interconnecting spaced source/drain regions and/or gate regions, and the resulting structures are provided. An etch-stop material such as silicon dioxide is deposited over the entire substrate on which the devices are formed. A layer of silicon is deposited over etch-stop material, and the silicon is selectively etched to reveal the etch-stop material at the regions to be connected. The etch-stop material at those regions is then removed. Following this a high-conductivity material, which is either a refractory metal or a silicide formed from layers of silicon and a refractory metal, is formed on the substrate connecting the spaced regions.

Structure for interconnecting different polysilicon zones on

Method and structure for interconnecting different polysilicon zones on

A process of patterning a conductive layer on a substrate avoiding webbing yet permitting high density patterning places two layers between the resist and the metal. The first layer is an antireflective coating such as titanium nitride applied to the metal. The second layer is a barrier comprising silicon such as sputtered silicon or SiO.sub.2. The barrier layer may also be a thin coating of spin-on glass. The barrier layer prevents interaction between the TiN and acid groups which are generated during exposure of the resist. With this structure in place the resist is applied, exposed and developed.

Bilayer metallization cap for photolithography

A process for forming a planarized, low sheet resistance FET. A gate stack is defined on an exposed surface of a semiconductor substrate, the gate stack including a gate mask disposed on a patterned polysilicon layer. First and second diffusion having first and second silicide electrodes are then formed on the substrate, to provide low sheet resistance source and drain electrodes. An insulating layer is then formed on the substrate, and is planarized to expose an upper surface of the gate mask. The gate mask is then removed in wet H.sub.3 PO.sub.4 to define an aperture in the insulating layer that exposes the polysilicon layer, and a conductive material is selectively grown on the substrate to provide a metal-strapped polysilicon gate electrode that is relatively co-planar with the planarized insulating layer.

Method of forming metal-strapped polysilicon gate electrode for FET

An annealing process carried out at 800.degree. C. in a wet O.sub.2 ambient permits the manufacture of a reliable storage capacitor wherein the dielectric layer is comprised of silicon oxynitride formed by low pressure chemical vapor deposition (LPCVD). The manufacturing process includes first depositing the silicon oxynitride film by LPCVD, second annealing in wet O.sub.2 at 800.degree. C. or N.sub.2 at 1000.degree. C., third forming an N-type region in the silicon substrate by As.sup.+ ion implantation through the silicon oxynitride film, fourth annealing in wet O.sub.2 at 800.degree. C., and fifth depositing an electrode.

Silicon oxynitride storage node dielectric

A method of fabricating a shared element semiconductor structure in which the insulating layer of a silicon-on-insulator structure is patterned to form a gate oxide. The bulk semiconductor underlying the insulating layer is defined into an FET (field-effect transistor) with its gate region below the gate oxide. The epitaxial layer above the insulating layer is defined into another FET with its drain region above the gate oxide, whereby the drain region also operates as the gate electrode for the bulk FET. Also described is a method of forming a silicon on insulator substrate with insulating layer usable as a gate oxide by means of bonding a silicon substrate to an oxidized epitaxial layer on another silicon seed substrate and then removing the seed substrate.

Method of fabricating silicon-on-insulator transistors with a shared

A method of forming a thin silicon layer upon which semiconductor devices may be constructed. An epitaxial layer is grown on a silicon substrate, and oxygen or nitrogen ions are implanted into the epitaxial layer in order to form a buried etch-stop layer therein. An oxide layer is grown on the epitaxial layer, and is used to form a bond to a mechanical support wafer. The silicon substrate is removed using grinding and/or HNA, the upper portions of the epitaxy are removed using EDP, EPP or KOH, and the etch-stop is removed using a non-selective etch. The remaining portions of the epitaxy forms the thin silicon layer. Due to the uniformity of the implanted ions, the thin silicon layer has a very uniform thickness.

Method of producing a thin silicon-on-insulator layer

A process for making complementary transistor devices in an epitaxial layer of a first conductivity type having a deep vertical isolation sidewall between the N and P channel transistors by providing a backfilled cavity in the epitaxial layer, the sidewalls of the cavity being coated with layers of material, the first layer being a silicate doped with the same conductivity type as the epitaxial layer in contact with the epitaxial layer and overcoated with an isolation and diffusion barrier layer, the second silicate layer doped to a conductivity opposite to that of the first layer and isolated therefrom by said isolation and diffusion barrier material. The cavity is backfilled with semiconductor material of a conductivity type opposite to that of the epitaxial layer and during this backfilling operation the dopants in the first and second layer outdiffuse into the epitaxial layer and into the backfill material respectfully to prevent the creations of parasitic channels.

Vertically isolated complementary transistors

Growing community of inventors

Essex, VT, United States of America

John R Abernathey