Synopsys, Inc.

Synopsis Incorporated

John Pasternak

James David Sproch

Pradip Subhana Jadhav

A circuit includes three PMOS transistors (PMOS) and three NMOS transistors (NMOS). The first PMOS has a source receiving a supply voltage and a gate receiving a first signal. The second PMOS has a source coupled to a drain of the first PMOS, a gate receiving a clock signal, and a drain generating a second signal. The third PMOS has a source receiving the supply voltage, and a drain coupled to the drain of the second PMOS. The first NMOS has a drain coupled to the drain of the second PMOS, and a gate coupled to a gate of the third PMOS. The second NMOS has a gate receiving the first signal, and a drain coupled to a source of the first NMOS. The third NMOS has a gate coupled to the gate of the third PMOS transistor, and a drain coupled to the drain of the third PMOS.

Single phase clock-gating circuit

A method for designing a standard cell, e.g. a multi-bit flip-flop, can include identifying a first set of transistors. This first set functions to source power or ground to circuits of the standard cell. A second set of transistors can be determined and correlated. This second set forms at least part of the first set of transistors. Each correlated group in the second set of transistors receives identical signals, e.g. scan enable, reset, and/or set signals, and provides a same sourcing. A third set of transistors can then be created. This third set has fewer transistors than the second set. The second set of transistors can be deleted in the standard cell. The third set of transistors can be connected to the circuits of the standard cell. This method can significantly extend circuit consolidation to improve the area benefit of multi-bit standard cells.

Multi-bit standard cells for consolidating transistors with selective sourcing

A latch is analyzed to determine meta-stable voltage bias points, which are then used to determine one or more of a settling time of the latch, a mean time before failure (MTBF) for a synchronizing circuit using the latch, or a regeneration time constant (Tau). The latch is analyzed by decomposing the latch circuit into a feed-forward circuit and a feedback circuit and then determining a first transfer function for the feed-forward circuit and a second transfer function for the feedback circuit. The transfer functions are then used to solve for meta-stable voltage bias points. The meta-stable voltage bias points are used as an initial condition for a simulation or measurement of the latch in order to measure settling time. The voltage curve during the settling time of the latch is used to calculate a value for Tau.

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San Jose, CA, United States of America

John Pasternak