Applied Materials, Inc.

John O Dukovic

Srinivas D Nemani

Dmitry Lubomirsky

Ellie Y Yieh

Sergey D Lopatin

Douglas A Buchberger, Jr

Praburam Gopalraja

Bhargav S Citla

David J Eaglesham

Nicolay Kovarsky

Charles Gay

Steven Hiloong Welch

Michael Xiaoxuan Yang

Peter G Borden

Hooman Hafezi

Zhi-Wen Sun

Robert Z Bachrach

Li Xu

Anzhong Chang

Shiyu Sun

You Wang

Nam Sung Kim

Aron Rosenfeld

John Busch

A method and apparatus for applying an electric field and/or a magnetic field to a photoresist layer without air gap intervention during photolithography processes is provided herein. The method and apparatus include a transfer device and a plurality of modules. The transfer device is configured to rotate a plurality of substrates between each of the modules, wherein one module includes a heating pedestal and another module includes a cooling pedestal. One module is utilized for inserting and removing the substrates from the system. At least the heating module is able to be sealed and filled with a process volume before applying the electric field.

Apparatus for post exposure bake of photoresist

A method and apparatus for applying an electric field and/or a magnetic field to a photoresist layer without air gap intervention during photolithography processes is provided herein. The method and apparatus include an electrode assembly and a base assembly. The electrode assembly includes a permeable electrode. The base assembly includes one or more process fluid channels disposed around a circumference of the substrate support surface and configured to fill a process volume with a process fluid. The electrode assembly is configured to apply an electric field to a substrate disposed within the process volume.

One or more embodiments described herein generally relate to patterning semiconductor film stacks. Unlike in conventional embodiments, the film stacks herein are patterned without the need of etching the magnetic tunnel junction (MTJ) stack. Instead, the film stack is etched before the MTJ stack is deposited such that the spin on carbon layer and the anti-reflective coating layer are completely removed and a trench is formed within the dielectric capping layer and the oxide layer. Thereafter, MTJ stacks are deposited on the buffer layer and on the dielectric capping layer. An oxide capping layer is deposited such that it covers the MTJ stacks. An oxide fill layer is deposited over the oxide capping layer and the film stack is polished by chemical mechanical polishing (CMP). The embodiments described herein advantageously result in no damage to the MTJ stacks since etching is not required.

Additive patterning of semiconductor film stacks

The present disclosure provide methods for forming nanowire structures with desired materials horizontal gate-all-around (hGAA) structures field effect transistor (FET) for semiconductor chips. In one example, a method of forming nanowire structures on a substrate includes forming a multi-material layer on a bottom structure on a substrate, wherein the multi-material layer includes repeating pairs of a first layer and a second layer, selectively removing the second layer from the multi-material layer from the substrate, and selectively oxidizing the bottom structure on the substrate after removing the second layer from the multi-material layer.

Methods for forming device isolation for semiconductor applications

A method for forming front contacts on a silicon solar cell which includes texture etching the front surface of the solar cell, forming an antireflective layer over the face, diffusing a doping material into the face to form a heavily doped region in valleys formed during the texture-etching of the face, depositing an electrically conductive material on the heavily doped regions in the valleys and annealing the solar cell.

Method of forming front contacts to a silicon solar cell without patterning

Embodiments of the invention contemplate the formation of a low cost solar cell using a novel electroplating apparatus and method to form a metal contact structure having metal lines formed using an electrochemical plating process. The apparatus and methods described herein remove the need to perform the often costly processing steps of performing a mask preparation and formation steps, such as screen printing, lithographic steps and inkjet printing steps, to form a contact structure. The resistance of interconnects formed in a solar cell device greatly affects the efficiency of the solar cell. It is thus desirable to form a solar cell device that has a low resistance connection that is reliable and cost effective. Therefore, one or more embodiments of the invention described herein are adapted to form a low cost and reliable interconnecting layer using an electrochemical plating process containing a common metal, such as copper. Embodiments of the invention may provide an apparatus and method of forming a solar cell device that utilizes a reusable masking device during one or more electrochemical deposition steps.

Precision printing electroplating through plating mask on a solar cell substrate

Embodiments of the invention contemplate the formation of a low cost solar cell using a novel high speed electroplating method and apparatus to form a metal contact structure having selectively formed metal lines using an electrochemical plating process. The apparatus and methods described herein remove the need to perform one or more high temperature screen printing processes to form conductive features on the surface of a solar cell substrate. The resistance of interconnects formed in a solar cell device greatly affects the efficiency of the solar cell. It is thus desirable to form a solar cell device that has a low resistance connection that is reliable and cost effective. Therefore, one or more embodiments of the invention described herein are adapted to form a low cost and reliable interconnecting layer using an electrochemical plating process containing a common metal, such as copper.

High-aspect ratio anode and apparatus for high-speed electroplating on a solar cell substrate

Generally, the process includes depositing a barrier layer and seed layer on a feature formed in a dielectric layer, performing a grafting process, initiating a copper layer and then filing the feature by use of a bulk copper fill process. Copper features formed according to aspects described herein have desirable adhesion properties to a barrier and seed layers formed on a semiconductor substrate and demonstrate enhanced electromigration and stress migration results in the fabricated devices formed on the substrate.

Grafted seed layer for electrochemical plating

A contact ring for an electrochemical plating system is provided. The contact ring includes an annular substrate supporting member, a plurality of radially positioned conductive substrate contact pins extending from the substrate supporting member, an annular conductive thief element attached to the substrate supporting member, and at least one source of electrical power in electrical communication with the contact pins and the conductive thief element.

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Palo Alto, CA, United States of America

John O Dukovic