International Business Machines Corporation

Jsr Corporation

John Michael Cotte

Wayne Martin Moreau

Kenneth John McCullough

John Patrick Simons

Charles Jesse Taft

Christopher Vincent Jahnes

David William Abraham

Richard Paul Volant

Keith Randal Pope

Hariklia Deligianni

Panayotis Constantinou Andricacos

Kenneth Jay Stein

John Ulrich Knickerbocker

Kevin Shawn Petrarca

Dario Leonardo Goldfarb

John Harold Magerlein

Laura Louise Kosbar

Paul Stephen Andry

Mahadevaiyer Krishnan

Cornelia K Tsang

Xiaoyan Shao

Madhav Datta

Cyril Cabral, Jr

Zhong-Xiang He

Douglas Duane Coolbaugh

Ebenezer E Eshun

Anthony K Stamper

Daniel C Edelstein

Josephine B Chang

Christian Lavoie

Kenneth Parker Rodbell

Stephen Mark Rossnagel

Robert L Wisnieff

Eric Jeffrey White

Carlos Juan Sambucetti

Anil Kumar Chinthakindi

Ravi F Saraf

Judith Marie Roldan

Jennifer L Lund

James Anthony Tornello

Matteo Flotta

Veeraraghavan S Basker

Bucknell Chapman Webb

Laertis Economikos

Duixian Liu

Deborah A Neumayer

Minhua Lu

Jeffrey Curtis Hedrick

Brian Paul Gaucher

Shyng-Tsong Chen

Shawn Anthony Hall

Michael F Lofaro

Hongbo Peng

Qiang Huang

Eric Peter Lewandowski

Chirag Suryakant Patel

Mary Beth Rothwell

Lynne Marie Gignac

Robert J Purtell

Cornelia Kang-I Tsang

Ullrich Richard Pfeiffer

Wei-Tsu Tseng

Wilma Jean Horkans

Ronald Dean Goldblatt

Oliver Dial

David E Eichstadt

Kathryn C Fisher

Hongqing Zhang

Lisa A Fanti

Ravindra V Shenoy

Devendra K Sadana

William R Tonti

Toshiharu Furukawa

Katherine Lynn Saenger

Kai D Feng

Zhen Zhang

Edmund Juris Sprogis

Hanyi Ding

Bomy A Chen

Xuefeng Liu

Satyanarayana Venkata Nitta

Vamsi Krishna Paruchuri

Balasubramanian S Haran

Harold John Hovel

Robert Allen Groves

Sung Kwon Kang

Seshadri Subbanna

Christopher Carr Parks

David Earle Seeger

Steven Erik Steen

Kunal Vaed

Henry Atkinson Nye, Iii

Tomohisa Konno

William Alfred Syverson

Tatsuya Yamanaka

Raul E Acosta

Philippe M Vereecken

Donna S Zupanski-Nielsen

Keith Thomas Kwietniak

Muir Kumph

A cryogenic electronics device includes a semiconductor chip. A substrate is flip-chip bonded to the semiconductor chip. A plurality of bump bonds are concentrated in a bump region of the semiconductor chip. A plurality of circuit elements are arranged in a predefined region of the semiconductor chip. The predefined region and the bump region are separate regions.

Electrical connections between dissimilar materials at cryogenic temperatures

A quantum computing chip device provides an edge based capacitive, intra-chip connection. A first chip includes a first signal line with a distal end positioned proximate to or on an edge of the first chip and a proximal end positioned away from the edge of the first chip. A second chip includes a second signal line with a distal end positioned proximate to or on an edge of the second chip and a proximal end positioned away from the edge of the second chip. The first signal line and the second signal line are configured to conduct a signal. The second signal line of the second chip is disposed in alignment for a capacitive bus connection to the first signal line of the first chip.

Edge capacitive coupling for quantum chips

An electronic structure includes a first substrate having a first under bump metallization (UBM) region and a second UBM region formed thereon. One or more solder bumps is deposited onto the first UBM region. A downstop formed on the second UBM region is wider, shallower and more rigid than any one of the solder bumps formed on the first UBM region. A second substrate is joined to the first substrate by the one or more solder bumps located on the first UBM region, and a height of the downstop limits a distance between at least one of the first substrate and the second substrate, or between an object and at least one of the first substrate and the second substrate.

Downstop and bump bonds formation on substrates

A semiconductor device comprises a first chip layer, having a first chip layer front-side and a first chip layer back-side, a qubit chip layer, having a qubit chip layer front-side and a qubit chip layer back-side, the qubit chip layer front-side operatively coupled to the first chip layer front-side with a set of bump-bonds, a set of through-silicon vias (TSVs) connected to at least one of: the first chip layer back-side or the qubit chip layer back-side and a cap wafer metal bonded to at least one of: the qubit chip layer back-side or the first chip layer back-side.

Create a protected layer for interconnects and devices in a packaged quantum structure

Techniques regarding qubit chip assemblies are provided. For example, one or more embodiments described herein can include an apparatus that can comprise a qubit chip positioned on an interposer chip. The apparatus can also comprise an electrical connector in direct contact with the interposer chip. The electrical connector can establish an electrical communication between a wire and a contact pad of the interposer chip that is coupled to the qubit chip.

Interposer chips and enclosures for quantum circuits

A method for forming an electronic chip assembly. A first metal plate is coupled to a first side of a substrate to form a backing plate. A first cavity is created extending through the substrate to extend at least to the first metal plate. An electronic component is bonded to the substrate such that the electronic component is located within the first cavity. A second metal plate, having a second cavity, is disposed to a second side of the substrate, and over the first cavity such that the electronic component is encased within the first and second cavities by the first and second metal plates.

Combined backing plate and housing for use in bump bonded chip assembly

A technique relates to a superconducting airbridge on a structure. A first ground plane, resonator, and second ground plane are formed on a substrate. A first lift-off pattern is formed of a first lift-off resist and a first photoresist. The first photoresist is deposited on the first lift-off resist. A superconducting sacrificial layer is deposited while using the first lift-off pattern. The first lift-off pattern is removed. A cross-over lift-off pattern is formed of a second lift-off resist and a second photoresist. The second photoresist is deposited on the second lift-off resist. A cross-over superconducting material is deposited to be formed as the superconducting airbridge while using the cross-over lift-off pattern. The cross-over lift-off pattern is removed. The superconducting airbridge is formed to connect the first and second ground planes by removing the superconducting sacrificial layer underneath the cross-over superconducting material. The superconducting airbridge crosses over the resonator.

Superconducting airbridge crossover using superconducting sacrificial material

A MEMS device comprises an electro mechanical element in a sealed chamber containing a gas comprising a reactive gas selected to react with any contaminants that may be present or formed on the operating surfaces of the device in a manner to maximize the electrical conductivity of the surfaces during operation of the device. The MEMS device may comprise a MEMS switch having electrical contacts as the operating surfaces. The reactive gas may comprise hydrogen or an azane, optionally mixed with an inert gas, or any combination of the gases. The corresponding process provides a means to substantially reduce or eliminate contaminants present or formed on the operating surfaces of MEMS devices in a manner to maximize the electrical conductivity of the surfaces during operation of the devices.

Use of a reactive, or reducing gas as a method to increase contact lifetime in micro contact MEMS switch devices

A semiconductor structure and methods of forming the semiconductor structure generally includes providing a thermocompression bonded superconducting metal layer sandwiched between a first silicon substrate and a second silicon substrate. The second substrate includes a plurality of through silicon vias to the thermocompression bonded superconducting metal layer. A second superconducting metal is electroplated into the through silicon vias using the thermocompression bonded superconducting metal layer as a bottom electrode during the electroplating process, wherein the filling is from the bottom upwards.

Semiconductor device including superconducting metal through-silicon-vias and method of making the same

A device has a first stack of thin films, the first stack of thin films having a first opposing surface and a first connection surface, wherein the first connection surface contacts a first superconducting region; a second stack of thin films, the second stack of thin films having a second opposing surface and a second connection surface, wherein the second connection surface contacts a second superconducting region; and a superconducting bump bond electrically connecting the first and second opposing surfaces, the superconducting bump bond maintaining a low ohmic electrical contact between the first and second opposing surfaces at temperatures below 100 degrees Kelvin, wherein at least one of the first or second superconducting regions comprise material with a melting point of at least 700 degrees Celsius.

Bump bonded cryogenic chip carrier

A technique relates to a device. First thin films are characterized by having a first opposing surface and a first connection surface in which the first connection surface is in physical contact with a first superconducting region. Second thin films are characterized by having a second opposing surface and a second connection surface in which the first and second opposing surfaces are opposite one another. The second connection surface is in physical contact with a second superconducting region. A solder material electrically connects the first and second opposing surfaces, and the solder material is characterized by maintaining a low ohmic electrical contact between the first and second opposing surfaces at temperatures below 100 degrees Kelvin. The first and second superconducting regions are formed of materials that have a melting point of at least 700 degrees Celsius.

A semiconductor structure and methods for the creation of solder bumps configured to carry a signal and solder bumps configured for ground planes and/or mechanical connections as well as methods for increasing reliability of a chip package generally include formation of multiple sized bump bonds on under bump metallization patterns and/or pads of the same dimension. The signal carrying solder bumps are larger in terms of diameter and bump height than solder bumps configured for ground plane and/or mechanical connections.

Multiple sized bump bonds

Semiconductor devices and electronics packaging methods include integrated circuit chips having redundant signal bond pads along with signal bond pads connected to the same signal port for non-destructive testing of the integrated circuit chips prior to packaging. Electrical testing is made via the redundant signal bond after which qualified integrated circuit chips can be attached to a pristine and bumped final interposer or printed circuit board to provide increased reliability to the assembled electronic package.

Non-destructive testing of integrated circuit chips

A structure has a first substrate bonded to a first under-bump metallization (UBM) structure, the first UBM structure comprising a first bonding region laterally surrounded by a first superconducting region. A second substrate is bonded to a second under-bump metallization (UBM) structure, the second UBM structure comprising a second bonding region laterally surrounded by a second superconducting region; and a superconducting solder material joins the first UBM structure to the second UBM structure.

Two-component bump metallization

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New Fairfield, CT, United States of America

John Michael Cotte