Spinnaker Semiconductor, Inc.

Avolare 2, LLC

Niron Magnetics, Inc.

John M Larson

John P Snyder

Francis Johnson

Yiming Wu

Richard W Greger

Fan Zhang

Kathryn Sara Damien

L Anderson Blackburn

Iron nitride nanoparticles and magnet materials made from iron nitride nanoparticles are described. The iron nitride nanoparticles have a core and a shell morphology. The shell is configured to provide a means to nitride the core. The magnetic materials are characterized as having an Msat greater than about 160 emu/g and a coercivity greater than about 700 Oe.

Coercivity-enhanced iron nitride nanoparticles with high saturation magnetization

Disclosed herein is a permanent magnet comprising: a plurality of aligned iron nitride nanoparticles wherein the iron nitride nanoparticles include &#x3b1;&#x2033;-FeNphase domains; wherein a ratio of integrated intensities of an &#x3b1;&#x2033;-FeN(004) x-ray diffraction peak to an &#x3b1;&#x2033;-&#x3b1;&#x2033;-FeN(202) x-ray diffraction peak for the aligned iron nitride nanoparticles is greater than at least 7%, wherein the diffraction vector is parallel to alignment direction, and wherein the iron nitride nanoparticles exhibit a squareness measured parallel to the alignment direction that is greater than a squareness measured perpendicular to the alignment direction.

Anisotropic iron nitride permanent magnets

A CMOS device and method of fabrication are disclosed. The present invention utilizes Schottky barrier contacts for source and/or drain contact fabrication within the context of a CMOS device and CMOS integrated circuits, to eliminate the requirement for halo/pocket implants, shallow source/drain extensions to control short channel effects, well implant steps, and complex device isolation steps. Additionally, the present invention eliminates the parasitic bipolar gain associated with CMOS device operation, reduces manufacturing costs, tightens control of device performance parameters, and provides for superior device characteristics as compared to the prior art. The present invention, in one embodiment, uses a silicide exclusion mask process to form the dual silicide Schottky barrier source and/or drain contact for the complimentary PMOS and NMOS devices forming the CMOS device.

Schottky barrier CMOS device and method

A CMOS device and method of manufacture is provided for producing an integrated circuit that is not susceptible to various soft errors such as single-event upsets, multi-bit upsets or single-event latchup. The CMOS device and method utilizes a new and novel well architecture in conjunction with metal source/drain electrodes to eliminate soft errors. In one embodiment, the CMOS device uses a first metal source/drain material for the NMOS device and a second metal source/drain material for the PMOS device. The CMOS device further uses a multi-layered well-structure with a shallow N-well and a buried P-well for the PMOS device and a shallow P-well and a buried N-well for the NMOS device.

Method of manufacturing a CMOS device with zero soft error rate

A device for regulating a flow of electric current and its manufacturing method are provided. The device includes metal-insulator-semiconductor source-drain contacts forming Schottky barrier or Schottky-like junctions to the semiconductor substrate. The device includes an interfacial layer between the semiconductor substrate and a metal source and/or drain electrode, thereby dynamically adjusting a Schottky barrier height by applying different bias conditions. The dynamic Schottky barrier modulation provides increased electric current for low drain bias conditions, reducing the sub-linear turn-on characteristic of Schottky barrier MOSFET devices and improving device performance.

Dynamic Schottky barrier MOSFET device and method of manufacture

The invention is directed to a device for regulating the flow of electric current with high dielectric constant gate insulating layer and a source and/or drain forming a Schottky contact or Schottky-like region with a substrate and its fabrication method. In one aspect, the gate insulating layer has a dielectric constant greater than the dielectric constant of silicon. In another aspect, the current regulating device may be a MOSFET device, optionally a planar P-type or N-type MOSFET, having any orientation. In another aspect, the source and/or drain may consist partially or fully of a silicide.

Metal source and drain transistor having high dielectric constant gate insulator

The present invention is a field effect transistor having a strained semiconductor substrate and Schottky-barrier source and drain electrodes, and a method for making the transistor. The bulk charge carrier transport characteristic of the Schottky barrier field effect transistor minimizes carrier surface scattering, which enables the strained substrate to provide improved power and speed performance characteristics in this device, as compared to conventional devices.

Field effect transistor having source and/or drain forming schottky or schottky-like contact with strained semiconductor substrate

CMOS device with zero soft error rate

Field effect transistor having source and/or drain forming Schottky or Schottky-like contact with strained semiconductor substrate

A method of fabricating a transistor device for regulating the flow of electric current is provided wherein the device has Schottky-barrier metal source-drain contacts. The method, in one embodiment, utilizes an isotropic etch process prior to the formation of the metal source-drain contacts to provide better control of the Schottky-barrier junction location to a channel region. The improvements from the controllability of the placement of the Schottky-barrier junction enables additional drive current and optimizes device performance, thereby significantly improving manufacturability.

Schottky-barrier mosfet manufacturing method using isotropic etch process

A MOSFET device and method of fabricating is provided. The MOSFET device and method of fabricating utilizes Schottky barrier contacts for source and/or drain contact fabrication within the context of a MOSFET device structure to eliminate the requirement for halo/pocket implants and shallow source/drain extensions to control short channel effects. Additionally, the MOSFET device and method unconditionally eliminates the parasitic bipolar gain associated with MOSFET fabrication, reduces manufacturing costs, tightens control of device performance parameters, and provides for superior device characteristics.

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Northfield, MN, United States of America

John M Larson