Freescale Semiconductor,inc.

Motorola Corporation

John M Grant

Tab Allen Stephens

Bich-Yen Nguyen

Gauri V Karve

Mark Douglas Hall

Marius K Orlowski

Suresh Venkatesan

Olubunmi O Adetutu

Chun-Li Liu

Srikanth Balaji Samavedam

Alexander Barr

Shawn George Thomas

Ted R White

Gregory S Spencer

Yeong-Jyh Tom Lii

Thomas Sachio Kobayashi

Glenn Charles Abeln

Jonathan L Cobb

Ross Edward Noble

Michael Rendon

Anna M Phillips

Yolanda S Musgrove

Al T Koh

Andrea Franke

A method of forming a semiconductor device comprises forming a control electrode over a portion of a semiconductor layer, forming recesses extending into the semiconductor layer on opposing sides of the control electrode, and forming doped regions in the semiconductor layer through the recesses. The doped regions form current electrode regions of the semiconductor device and each doped region extends into the semiconductor layer from at least a base of a recess. The method further comprises forming, after forming the doped regions, strained semiconductor regions in the recesses, wherein a junction between each doped region and the semiconductor layer is formed below an interface between a strained semiconductor region and the semiconductor layer.

Method of forming a semiconductor device and semiconductor device

A semiconductor device is formed. A first gate dielectric layer is formed over the semiconductor layer. A first conductive layer is formed over the first gate dielectric. A first separation layer is formed over the first conductive layer. A trench is formed in the semiconductor layer to separate the first mesa and the second mesa. The trench is filled with an isolation material to a height above a top surface of the first conductive layer. The first conductive layer is removed from the second mesa. A second conductive layer is formed over the first separation layer of the first mesa and over the second mesa. A planarizing etch removes the second conductive layer from over the first mesa. A first transistor of a first type is formed in the first mesa, and a second transistor of a second type is formed in the second mesa.

Separate layer formation in a semiconductor device

A semiconductor device is formed on a semiconductor layer. A gate dielectric layer is formed over the semiconductor layer. A layer of gate material is formed over the gate dielectric layer. The layer of gate material is patterned to form a gate structure. Using the gate structure as a mask, an implant into the semiconductor layer is performed. To form a first patterned gate structure and a trench in the semiconductor layer surrounding a first portion and a second portion of the semiconductor layer and the gate, an etch through the gate structure and the semiconductor layer is performed. The trench is filled with insulating material.

Trench formation in a semiconductor material

A semiconductor process and apparatus provide a planarized hybrid substrate () by thermally oxidizing SOI sidewalls () in a trench opening () to form SOI sidewall oxide spacers () which are trimmed while etching through a buried oxide layer () to expose the underlying bulk substrate () for subsequent epitaxial growth of an epitaxial semiconductor layer (). In this way, SOI sidewall oxide spacers () are formed that prevent epitaxial SOI sidewalls from being formed in the trench opening () during the epitaxial growth step, and that can be readily removed during any subsequent STI etch process

Dual substrate orientation or bulk on SOI integrations using oxidation for silicon epitaxy spacer formation

A semiconductor device includes a single crystal substrate and a dielectric layer overlying the substrate. The dielectric layer includes at least one opening having a first portion and an overlying second portion. The first portion has a depth and width, such that an aspect ratio of the depth to width is greater than one. The semiconductor device further includes a first material having a first portion and a second portion, the first portion of the first material filling the first portion of the at least one opening. Defects for relaxing strain at an interface between the first material and the substrate material exist only within the first portion of the first material due to the aspect ratio being greater than one. The second portion of the first material is substantially defect free. Furthermore, the second portion of the first material and an overlying second material different than the first material fill the overlying second portion of the at least one opening. The second material has a thickness which is less than a critical thickness to maintain the second material in a strained state. The strained second material functions as a channel for charge carriers.

Semiconductor device incorporating a defect controlled strained channel structure and method of making the same

An insulating layer () is formed over a stack () of materials and a semiconductor substrate () and an implant is performed through the insulating layer into the semiconductor substrate. In one embodiment, spacers () are formed over the insulating layer (), the insulating layer () is etched, and heavily doped regions () are formed adjacent the spacers. The spacers () are then removed and extension regions () and optional halo regions () are formed by implanting through the insulating layer (). In one embodiment, the insulating layer () is in contact with the semiconductor substrate (). In one embodiment, the stack () is a gate stack including a gate dielectric (), a gate electrode (), and an optional capping layer (). The insulating layer () may include nitrogen, such as silicon nitride and aluminum nitride. In another embodiment, the insulating layer () may be hafnium oxide.

Semiconductor device having an insulating layer and method for forming

A method of forming a semiconductor device so as to provide the device inverted isolation trenches with convex sidewalls. Initially, a plurality of composite isolation posts () are formed on a substrate () through successive deposition, lithography, and etching steps. The posts comprise a bottom layer () of silicon dioxide and an overlying etch-stop layer of silicon nitride (). An insulating material () is then deposited over the isolation posts and areas of the substrate. Isolation structures () are established by etching the insulating material to form convex sidewall spacers () at the vertical walls of the isolation posts. Active areas () between spacers are filled with semiconductor material. In an embodiment, a strained cap layer () may be imposed on the active areas. The strained cap layer has a lattice constant that is different from the lattice constant of the semiconductor material.

Inverted isolation formed with spacers

A semiconductor structure includes a substrate comprising a first relaxed semiconductor material with a first lattice constant. A semiconductor device layer overlies the substrate, wherein the semiconductor device layer includes a second relaxed semiconductor material with a second lattice constant different from the first lattice constant. In addition, a dielectric layer is interposed between the substrate and the semiconductor device layer, wherein the dielectric layer includes a programmed transition zone disposed within the dielectric layer for transitioning between the first lattice constant and the second lattice constant. The programmed transition zone includes a plurality of layers, adjoining ones of the plurality of layers having different lattice constants with one of the adjoining ones having a first thickness exceeding a first critical thickness required to form defects and another of the adjoining ones having a second thickness not exceeding a second critical thickness. Each adjoining layer of the plurality of layers forms an interface for promoting defects in the transition zone to migrate to and terminate on an edge of the programmed transition zone. A method of making the same is also disclosed.

Semiconductor structure with different lattice constant materials and method for forming the same

A semiconductor substrate has features extending above the surface. In one use, these features are gate stacks in which the gate is polysilicon to be replaced by metal. A dielectric is deposited over the substrate and the gate stacks having contours corresponding to the features. The desired structure prior to replacing the polysilicon gates is for the dielectric to be planar and even with the top of the gate stack. This is difficult to achieve with conventional CMP procedures because of varying polish rates based on the area and density of these features. The desired planarity is achieved by first depositing a conformal sacrificial layer. A CMP step using light downforce results in exposing and planarizing the underlying contours of the dielectric layer. A subsequent CMP step using higher downforce achieves the desired planar structure by providing a greater polish rate for the dielectric layer than for the sacrificial layer.

Method for making a semiconductor device by variable chemical mechanical polish downforce

A metal gate structure is formed by depositing a gate dielectric, a gate electrode, a stop layer, and a metal layer within a gate trench and removing the portions of the layers that lie outside the gate trench. A first polish or etch process is used to remove a portion of the metal layer selective to the stop layer. A second polish or etch process is used to remove portions of the gate dielectric, the gate electrode, the stop layer and the metal layer which lie outside the gate trench after the first polish or etch process. The resulting structure increases the uniformity and non-planarity of the top surface of the metal gate structure.

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Austin, TX, United States of America

John M Grant