International Business Machines Corporation

John L Mauer, Iv

Harsaran S Bhatia

Narasipur G Anantha

Bernard M Kemlage

Richard C Joy

Laura B Rothman

Joseph S Logan

Santosh Prasad Gaur

Geraldine C Schwartz

Charles L Standley

David Earle Seeger

Michel S Michail

Ronald Anthony DellaGuardia

Homi G Sarkary

Ollie C Woodard

Alwin E Michel

Reginald F Lever

The present invention provides a method for determining the development endpoint in a X-ray lithographic process. Endpoint is determined by visually observing resist test field patterns through a microscope during the developing step. During the developing, changing test field patterns are formed because test field locations each had been exposed simultaneously to different radiation doses. These different doses are produced when radiation passes through a mask containing a plurality of different size radiation attenuators. When the changing test field pattern matches a known pattern, which is correlated to the desired development endpoint, the workpiece is removed from the developing step.

Resist development endpoint detection for X-ray lithography

A method is disclosed for fabricating a small area, self aligned guard ring in a Schottky barrier diode. A vertically-walled hole is anisotropically etched completely through a dielectric layer on a silicon substrate. A layer of doped polycrystalline silicon is deposited over the apertured dielectric layer. The polycrystalline silicon is reactively ion etched away to leave only a lining about the perimeter of the hole in the dielectric layer. The structure is heated to diffuse the dopant from the lining into the substrate. Schottky diode metal is deposited on the substrate exposed through the lined aperture in the dielectric layer.

Schottky diode having limited area self-aligned guard ring and method

Method for making Schottky diode having limited area self-aligned guard

An integrated circuit structure having substrate contacts formed as a part of the isolation structure and the method to form such structure is described. The integrated circuit structure is composed of a monocrystalline silicon body having a pattern of dielectric isolation surrounding regions of the monocrystalline silicon in the body. The dielectric isolation pattern includes a recessed dielectric portion at and just below the surface of the integrated circuit and a deep portion which extends through the recessed dielectric portion and extends further into the monocrystalline silicon body than the recessed portion. A highly doped polycrystalline silicon substrate contact is located within the deep portion of the pattern of isolation. The substrate contact extends from the surface of the pattern of isolation down to the bottom of the deep portion of the isolation where the contact electrically connects to the silicon body. Any of a variety of integrated circuit device structures may be incorporated within the monocrystalline silicon regions. These devices include bipolar transistors, field effect transistors, capacitors, diodes, resistors and the like.

Isolation for high density integrated circuits

An electron beam method and apparatus, for writing patterns, such as on semiconductor wafers, in which the writing field is divided into a large number of overlapping subfields with a predetermined periodicity. Subfield to subfield moves are made in a stepped sequential scan, such as raster, while patterns, within a subfield, are addressed using vector scan and written using a sequential scan. Significant improvement in throughput results by the use of this electron beam method and apparatus which preferably employs magnetic deflection for the sequential scanning the subfields and electric deflection for vector scanning within the subfield.

Electron beam system

An integrated circuit structure having substrate contacts formed as a part of the isolation structure and method for making the same is described. The integrated circuit structure is composed of a monocrystalline silicon body having a pattern of dielectric isolation surrounding regions of the monocrystalline silicon in the body. The dielectric isolation pattern includes a recessed dielectric portion at and just below the surface of the integrated circuit and a deep portion which extends from the side of the recessed dielectric portion opposite to that portion at the surface of said body into the monocrystalline silicon body. A highly doped polycrystalline silicon substrate contact is located within the deep portion of the pattern of isolation. At certain locations the deep portion of the pattern extends to the surface of the silicon body where interconnection metallurgy can electrically contact the polycrystalline silicon so as to form a substrate contact to the bottom of the deep portion of the isolation where the contact electrically connects to the silicon body. Any of a variety of integrated circuit device structures may be incorporated within the monocrystalline silicon regions. These devices include bipolar transistors, field effect transistors, capacitors, diodes, resistors and the like.

Use of a dual composite mask for a lift-off multi-layered structure process in which a base component layer acts as an etch stop for reactive ion etching of overlying layers.

Planar multi-level metal process with built-in etch stop

A method for eliminating deposited residues, for example polysilicon residue, on vertical silicon dioxide sidewalls that have been reactive ion etched includes reshaping the sidewalls to have a slope of at least +30.degree. relative to the vertical direction of the sidewall.

Method for avoiding residue on a vertical walled mesa

A planar deep oxide isolation process for providing deep wide silicon dioxide filled trenches in the planar surface of a silicon semiconductor substrate, said process comprising the steps:

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South Kent, CT, United States of America

John L Mauer, Iv