Globalfoundries U.S. Inc.

International Business Machines Corporation

Globalfoundries Inc.

Globalfoundries Singapore Pte. Ltd.

Globalpoundries U.S. Inc.

John Joseph Pekarik

Vibhor Jain

Qizhi Liu

Anthony K Stamper

Steven M Shank

John J Ellis-Monaghan

Judson Robert Holt

David Louis Harame

James William Adkisson

Alvin Jose Joseph

Yun Shi

Renata A Camillo-Castillo

Alexander M Derrickson

Shyue Seng Tan

William F Clark, Jr

Xinshu Cai

Edward J Nowak

Kevin K Chan

Herbert Lei Ho

Jed Hickory Rankin

Yanli Zhang

Mark David Jaffe

Marwan H Khater

Hong Yu

Yung Fu Chong

Claude Ortolland

David R Greenberg

Basanth Jagannathan

Peng Cheng

Xudong Wang

Kien Seen Daniel Chong

Kenneth J Stein

Dureseti Chidambarrao

Andres Bryant

Shreesh Narasimha

Robert K Leidy

Randy William Mann

Richard Quimby Williams

Stephen Ellinwood Luce

Christopher Stephen Putnam

Viorel C Ontalus

Alan Bernard Botula

Venkatesh P Gopinath

David Michael Fried

Jerome Brett Lasky

Ramana Murty Malladi

Francis Roger White

James Randall Elliott

Christopher M Schnabel

Anupam Dutta

Rui Tze Toh

Archibald John Allen

Oscar Restrepo

Pernell Dongmo

Jorg Scholvin

Jeffrey W Sleight

Robert J Gauthier, Jr

Yusheng Bian

Charles W Koburger, Iii

Kirk David Peterson

Jeffrey Bowman Johnson

Robert Mark Rassel

Jagar Singh

James Stuart Dunn

James Spiros Nakos

Michael Joseph Zierak

Anil Kumar Chinthakindi

Gregory Gower Freeman

Zhenyu Hu

Richard A Phelps

David C Pritchard

James Allan Bruce

Jonathan Daniel Chapple-Sokol

Peter B Gray

Ramsey M Hazbun

Cameron E Luce

Michael James Lercel

Vikas Kumar Kaushal

Humberto Campanella Pineda

Edward W Sengle

Blaine Jeffrey Gross

Walter J Varhue

Vvss Satyasuresh Choppalli

Michael L Kerbaugh

Christopher Durcan

Tayel Nesheiwat

Sebastien Lasserre

V V S S Satyasuresh Choppalli

Jeffrey Johnson

Structures that include bipolar junction transistors and methods of forming such structures. The structure comprises a substrate having a top surface, a trench isolation region in the substrate, and a base layer on the top surface of the substrate. The base layer extending across the trench isolation region. A first bipolar junction transistor includes a first collector in the substrate and a first emitter on a first portion of the first base layer. The first portion of the first base layer is positioned between the first collector and the first emitter. A second bipolar junction transistor includes a second collector in the substrate and a second emitter on a second portion of the first base layer. The second portion of the first base layer is positioned between the second collector and the second emitter.

Array arrangements of vertical bipolar junction transistors

Structures that include bipolar junction transistors and methods of forming such structures. The structure comprises a semiconductor layer, a substrate, and a dielectric layer disposed between the semiconductor layer and the substrate. The structure further comprises a first bipolar junction transistor including a first collector in the substrate, a first emitter, and a first base layer. The first base layer extends through the dielectric layer from the first emitter to the first collector. The structure further comprises a second bipolar junction transistor including a second collector in the substrate, a second emitter, and a second base layer. The second base layer extends through the dielectric layer from the second emitter to the second collector. The second base layer is connected to the first base layer by a section of the semiconductor layer to define a base line.

Bipolar junction transistor arrays

Structures for a junction field-effect transistor and methods of forming a structure for a junction field-effect transistor. The structure comprises a first gate on a top surface of a semiconductor substrate, a second gate beneath the top surface of the semiconductor substrate, and a channel region in the semiconductor substrate. The first gate is positioned between a source and a drain, and the channel region positioned between the first gate and the second gate.

Junction field-effect transistors

Structures for a heterojunction bipolar transistor and methods of forming a structure for a heterojunction bipolar transistor. The structure comprises an emitter, a collector including a first section, a second section, and a third section positioned in a first direction between the first section and the second section, and an intrinsic base disposed in a second direction between the emitter and the third section of the collector. The structure further comprises a stress layer including a section positioned to overlap with the emitter, the intrinsic base, and the collector. The section of the stress layer is surrounded by a perimeter, and the first and second sections of the collector are each positioned adjacent to the perimeter of the stress layer.

Heterojunction bipolar transistors with a cut stress liner

A semiconductor device includes a first substrate, a second substrate bonded to the first substrate, and at least one thermally conductive structure that extends through a portion of the first substrate and a portion of the second substrate and is vertically aligned with an active region of the first substrate. The at least one thermally conductive structure is electrically insulated from electrically active structures in the semiconductor device. The thermally conductive structure acts as a heat sink to transfer heat from the active region.

Heat sink for face bonded semiconductor device

The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors (HBTs) with a buried trap rich isolation region and methods of manufacture. The structure includes: a first heterojunction bipolar transistor; a second heterojunction bipolar transistor; and a trap rich isolation region embedded within a substrate underneath both the first heterojunction bipolar transistor and the second heterojunction bipolar transistor.

Heterojunction bipolar transistor with buried trap rich isolation region

Structures for a heterojunction bipolar transistor and methods of forming a structure for a heterojunction bipolar transistor. The structure comprises an intrinsic base including a first semiconductor layer, a collector including a second semiconductor layer, and an emitter including a third semiconductor layer. The first semiconductor layer, which comprises silicon-germanium, includes a first portion and a second portion adjacent to the first portion. The second semiconductor layer includes a portion on the first portion of the first semiconductor layer, and the third semiconductor layer includes a portion on the second portion of the first semiconductor layer. The structure further comprises a dielectric spacer laterally between the portion of the second semiconductor layer and the portion of the third semiconductor layer.

Heterojunction bipolar transistors with terminals having a non-planar arrangement

The present disclosure relates to semiconductor structures and, more particularly, to transistor with wrap-around extrinsic base and methods of manufacture. The structure includes: a substrate; a collector region within the substrate; an emitter region over the substrate and which comprises silicon based material; an intrinsic base; and an extrinsic base overlapping the emitter region and the intrinsic base; an extrinsic base overlapping the emitter region and the intrinsic base; and an inverted 'T' shaped spacer which separates the emitter region from the extrinsic base and the collector region from the emitter region.

Transistor with wrap-around extrinsic base

The present disclosure relates to semiconductor structures and, more particularly, to bipolar transistors and methods of manufacture. The structure includes: an intrinsic base region; an emitter region above the intrinsic base region; a collector region under the intrinsic base region; and an extrinsic base region comprising metal material, and which surrounds the intrinsic base region and the emitter region.

Bipolar transistors

Embodiments of the disclosure provide a lateral bipolar transistor structure with a superlattice layer and methods to form the same. The bipolar transistor structure may have a semiconductor layer of a first single crystal semiconductor material over an insulator layer. The semiconductor layer includes an intrinsic base region having a first doping type. An emitter/collector (E/C) region may be adjacent the intrinsic base region and may have a second doping type opposite the first doping type. A superlattice layer is on the E/C region of the semiconductor layer. A raised E/C terminal, including a single crystal semiconductor material, is on the superlattice layer. The superlattice layer separates the E/C region from the raised E/C terminal.

Lateral bipolar transistor structure with superlattice layer and method to form same

The present disclosure relates to semiconductor structures and, more particularly, to transistor with wrap-around extrinsic base and methods of manufacture. The structure includes: a substrate; a collector region within the substrate; an emitter region over the substrate and which comprises mono-crystal silicon based material; an intrinsic base under the emitter region and comprising semiconductor material; and an extrinsic base surrounding the emitter and over the intrinsic base.

The present disclosure relates to semiconductor structures and, more particularly, to a heterojunction bipolar transistor having an emitter base junction with a silicon-oxygen lattice interface and methods of manufacture. The device includes: a collector region buried in a substrate; shallow trench isolation regions, which isolate the collector region buried in the substrate; a base region on the substrate and over the collector region; an emitter region composed of a single crystalline of semiconductor material and located over with the base region; and an oxide interface at a junction of the emitter region and the base region.

Heterojunction bipolar transistor with emitter base junction oxide interface

The disclosure provides a lateral bipolar transistor structure with a base layer over a semiconductor buffer, and related methods. A lateral bipolar transistor structure may include an emitter/collector (E/C) layer over an insulator. The E/C layer has a first doping type. A semiconductor buffer is adjacent the insulator. A base layer is on the semiconductor buffer and adjacent the E/C layer, the base layer including a lower surface below the E/C layer and an upper surface above the E/C layer. The base layer has a second doping type opposite the first doping type.

Lateral bipolar transistor structure with base over semiconductor buffer and related method

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Underhill, VT, United States of America

John Joseph Pekarik