Raytheon Company

John J Mosca

William E Hoke

Peter S Lyman

A semiconductor structure, comprising: a substrate; a first aluminum nitride (AlN) layer having an aluminum/reactive nitride (Al/N) flux ratio less than 1 disposed on the substrate; and a second AlN layer having an Al/reactive N flux ratio greater than 1 disposed on the first AlN layer. The substrate is a compound of silicon wherein the first AlN layer is substantially free of silicon.

Gallium nitride high electron mobility transistor structure

The invention provides a method of fabricating a wafer including growing a single crystal layer comprising a III-V compound in a first chamber at a temperature above 350&deg; C. A temperature of a surface of the single crystal layer is reduced to below about 350&deg; C. in the first chamber. An indium arsenide layer is deposited on the single crystal layer, to form an intermediate structure, in the first chamber at a temperature below 350&deg; C. and above 100&deg; C. The intermediate structure is transferred to a second chamber. A surface of the intermediate structure is heated to a temperature above about 600&deg; C. to remove substantially all of the indium arsenide layer and impurities collected in the indium arsenide layer during the transfer to the second chamber. Another material is deposited on the single crystal layer in the second chamber.

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Carlisle, MA, United States of America

John J Mosca