Varian Semiconductor Equipment Associates, Inc.

Tel Epion Corporation

Applied Materials, Inc.

Tokyo Electron Limited

Epion Corporation

John J Hautala

Simon Ruffell

Tristan Yonghui Ma

Steven Robert Sherman

Noel Russell

Huixiong Dai

Morgan Evans

Anthony Renau

Sony Varghese

Adam Brand

Maureen Petterson

Johannes F M Westendorp

Ludovic Godet

Joseph C Olson

Johannes M Van Meer

Armin Saeedi Vahdat

Robert Michael Geffken

Martin D Tabat

John Gumpher

Wesley J Skinner

Min Gyu Sung

Arthur J Learn

John O Borland

Nathan E Baxter

Kelvin Chan

Rutger Meyer Timmerman Thijssen

Costel Biloiu

Alexandre Likhanskii

Christopher R Hatem

Michael A Graf

Shurong Liang

Matthew C Gwinn

Naushad K Variam

Rajesh Prasad

Kevin R Anglin

Tsung-Liang Chen

Christopher A Rowland

Alexander C Kontos

Yan Shao

M Arif Zeeshan

Yan Zhang

Thomas G Tetreault

Shantanu Kallakuri

Jun Lang

Joe Olson

Charith Nanayakkara

Srinivas D Nemani

Qintao Zhang

Sipeng Gu

Joseph T Hillman

Peter F Kurunczi

Yi Zheng

Sean R Kirkpatrick

Christopher W Campbell

Allen R Kirkpatrick

Kyu-Ha Shim

Jerald P Dykstra

Michael E Mack

Andrew Michael Waite

Daniel Distaso

Steven P Caliendo

Brian S Freer

Xianfeng Lu

Thomas R Omstead

Heyun Yin

Arvind Kumar

Yuri Erokhin

David Richard Swenson

Fareen Adeni Khaja

Robert Masci

Gregory Herdt

Edmund Burke

Ethan A Wright

Boya Cui

Swaminathan Srinivasan

Koji Yamashita

Mitchell A Carlson

John G North

A method may include providing a set of features in a mask layer, wherein a given feature comprises a first dimension along a first direction, second dimension along a second direction, orthogonal to the first direction, and directing an angled ion beam to a first side region of the set of features in a first exposure, wherein the first side region is etched a first amount along the first direction. The method may include directing an angled deposition beam to a second side region of the set of features in a second exposure, wherein a protective layer is formed on the second side region, the second side region being oriented perpendicularly with respect to the first side region. The method may include directing the angled ion beam to the first side region in a third exposure, wherein the first side region is etched a second amount along the first direction.

Techniques and apparatus for selective shaping of mask features using angled beams

Approaches for reducing GIDL are disclosed. In one example, a method of forming a DRAM device may include forming a trench in a substrate layer, providing a first gate oxide layer along a sidewall and a bottom surface of the trench, and forming a first gate material within the trench. The method may further include removing the first gate oxide layer along an upper portion of the sidewall of the trench by delivering ions into the upper portion of the trench at a non-zero angle relative to a perpendicular extending from an upper surface of the substrate layer, and forming a second gate oxide layer along the upper portion of the sidewall of the trench, wherein a first dielectric constant of the first gate oxide layer is greater than a second dielectric constant of the second gate oxide layer.

Devices and methods for DRAM leakage reduction

Disclosed are approaches for forming semiconductor device layers. One method may include forming a plurality of openings in a semiconductor structure, and forming a film layer atop the semiconductor structure by delivering a material at a non-zero angle relative to a normal extending perpendicular from an upper surface of the semiconductor structure. The film layer may be formed along the upper surface of the semiconductor structure without being formed along a sidewall of each opening of the plurality of openings, wherein an opening though the film layer remains above each opening of the plurality of openings.

Method for depositing layers directly adjacent uncovered vias or contact holes

A ribbon beam plasma enhanced chemical vapor deposition (PECVD) system comprising a process chamber containing a platen for supporting a substrate, and a plasma source disposed adjacent the process chamber and adapted to produce free radicals in a plasma chamber, the plasma chamber having an aperture associated therewith for allowing a beam of the free radicals to exit the plasma chamber, wherein the process chamber is maintained at a first pressure and the plasma chamber is maintained at a second pressure greater than the first pressure for driving the free radicals from the plasma chamber into the process chamber.

Ribbon beam plasma enhanced chemical vapor deposition system for anisotropic deposition of thin films

A method may include providing an array of patterned features on a substrate, the array of patterned features characterized by a spacing. The method may include directing a sputtering species in a first exposure to the array of patterned features, wherein an upper portion of a patterned feature of the array of patterned features forms a protrusion, extending towards an adjacent patterned feature, of the array of patterned features. The method may also include directing a depositing species in a second exposure to the array of patterned features, wherein an array of voids is formed between adjacent patterned features.

Multi process air gap formation

Embodiments herein include void-free material depositions on a substrate (e.g., in a void-free trench-filled (VFTF) component) obtained using directional etching to remove predetermined portions of a seed layer covering the substrate. In several embodiments, directional etching followed by selective deposition can enable fill material (e.g., metal) patterning in tight spaces without any voids or seams. Void-free material depositions may be used in a variety of semiconductor devices, such as transistors, dual work function stacks, dynamic random-access memory (DRAM), non-volatile memory, and the like.

Techniques for void-free material depositions

A semiconductor manufacturing process and semiconductor device having an airgap to isolate bottom implant portions of a substrate from upper source and drain device structure to reduce bottom current leakage and parasitic capacitance with an improved scalability on n-to-p spacing scaling. The disclosed device can be implanted to fabricate nanosheet FET and other such semiconductor device. The airgap is formed by etching into the substrate, below a trench in a vertical and horizontal direction. The trench is then filled with dielectric and upper device structure formed on either side of the dielectric filler trench.

Directional etch for improved dual deck three-dimensional NAND architecture margin

Disclosed are approaches for forming semiconductor device cavities. One method may include providing a set of semiconductor structures defining an opening, wherein the opening has a first opening width along an upper portion of the opening and a second opening width along a lower portion of the opening, the first opening width being greater than the second opening width. The method may further include forming a blocking layer along the set of semiconductor structures by delivering a material at a non-zero angle of inclination relative to a normal extending perpendicular from a top surface of the set of semiconductor structures. The blocking layer may be formed along the upper portion of the opening without being formed along the lower portion of the opening, and wherein an opening through the blocking layer is present above the opening.

High aspect ratio taper improvement using directional deposition

Disclosed are approaches for forming semiconductor device cavities using directional dielectric deposition. One method may include providing a plurality of semiconductor structures and a plurality of trenches of a semiconductor device, and forming a dielectric atop the plurality of semiconductor structures by delivering a dielectric material at a non-zero angle of inclination relative to a normal extending perpendicular from a top surface of the plurality of semiconductor structures. The dielectric may be further formed by delivering the dielectric material at a second non-zero angle of inclination relative to the normal extending perpendicular from the top surface of the plurality of semiconductor structures.

Semiconductor device cavity formation using directional deposition

A method of patterning a substrate. The method may include providing a surface feature on the substrate, the surface feature having a first dimension along a first direction within a substrate plane, and a second dimension along a second direction within the substrate plane, wherein the second direction is perpendicular to the first direction; and directing first ions in a first exposure to the surface feature along the first direction at a non-zero angle of incidence with respect to a perpendicular to the substrate plane, in a presence of a reactive ambient containing a reactive species; wherein the first exposure etches the surface feature along the first direction, wherein after the directing, the surface feature retains the second dimension along the second direction, and wherein the surface feature has a third dimension along the first direction different than the first dimension.

Techniques to engineer nanoscale patterned features using ions

Disclosed are approaches for 3D NAND structure fabrication. One method may include providing a stack of layers comprising a first and second plurality of layers, and forming a plurality of trenches in the stack of layers, wherein each of the trenches includes a tiered sidewall. A first trench may be formed to a first depth, and a second trench may be formed to a second depth, which is greater than the first depth. The method may further include forming a liner within the trenches, wherein the liner is deposited at a non-zero angle of inclination relative to a normal extending perpendicular from the top surface of the stack of layers. The liner may have a first thickness along the tiered sidewall of the first trench and a second thickness along the tiered sidewall of the second trench, wherein the first thickness is greater than the second thickness.

Wordline contact formation in NAND devices

A workpiece processing apparatus allowing independent control of the voltage applied to the shield ring and the workpiece is disclosed. The workpiece processing apparatus includes a platen. The platen includes a dielectric material on which a workpiece is disposed. A bias electrode is disposed beneath the dielectric material. A shield ring, which is constructed from a metal, ceramic, semiconductor or dielectric material, is arranged around the perimeter of the workpiece. A ring electrode is disposed beneath the shield ring. The ring electrode and the bias electrode may be separately powered. This allows the surface voltage of the shield ring to match that of the workpiece, which causes the plasma sheath to be flat. Additionally, the voltage applied to the shield ring may be made different from that of the workpiece to compensate for mismatches in geometries. This improves uniformity of incident angles along the outer edge of the workpiece.

Extreme edge uniformity control

Disclosed herein are methods for forming MOSFETs. In some embodiments, a method may include providing a device structure including a plurality of trenches, forming a gate spacer layer over the device structure, and removing the gate spacer layer from a top surface of the device structure and from a first section of each of the plurality of trenches, wherein a portion of the gate spacer layer remains along a second section of each of the plurality of trenches. The method may further include forming a gate oxide layer along the first section of each of the plurality of trenches and along the portion of the gate spacer layer.

Ion implantation to form step-oxide trench MOSFET

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Beverly, MA, United States of America

John J Hautala