Harris Corporation

Fairchild Semiconductor Corporation

Intersil Corporation

John J Hackenberg

Jack H Linn

Jun Zeng

George V Rouse

John T Gasner

Donald Frank Hemmenway

Lawrence G Pearce

Patrick Anthony Begley

David A Decrosta

Jeanne Marie McNamara

Linda Susan Brush

Linda S Brush

Choong S Rhee

A power trench MOS-gated transistor is constructed with a buried gate to source dielectric inside a gate trench region. In the innovative device, a thick oxide (grown or deposited) is used to define the height of the trench walls. A body region is initially formed by selective epitaxial growth and etch back. Source regions are formed also by selective epitaxial growth. The body is finally formed by selective epitaxial growth and etch back. The oxide is removed from the trench, the trench walls are oxidized to form a gate oxide, and doped polysilicon fills the trench to form a gate. By the formation of the source region using the spacer etch, this process simplifies the fabrication of power trench gated devices, and provides for increased contact surface area without increasing device size.

Power trench transistor device source region formation using silicon spacer

A method of smoothing irregularities in a surface of a semiconductor device using flowable particles which are dispersed onto the surface of the semiconductor device. The irregularities in the surface of the semiconductor device are filled with flowable particles smaller in size than the irregularities which are to be smoothed, and the particles are thereafter heated so that they flow and fill the irregularities, forming a smooth layer of flowable particle material which does not require polishing. The flowable particles may be mixed with non-flowable particles which are encapsulated in the layer of flowable particle material to form a homogeneous layer. The non-flowable particles may be augmentors which modify the properties of the layer. The particles may be dispersed with a spin-on process.

Planarization method by use of particle dispersion and subsequent

A device and method for removing contaminants from semiconductor wafers and from the interior of wafer processing chambers in which the temperature inside the chambers is raised to sufficiently high levels for short time periods. In a wafer etching chamber, heat cleaning is performed after wafer removal and lessens the required frequency of other cleaning methods and in doing so reduces the time the chamber is unavailable. In a mask removal chamber, heat cleaning is performed with the wafer in the chamber and while still under vacuum conditions, thereby driving contaminants off of both the wafer and the chamber interior. The wafer cleaning is performed prior to exposure to atmospheric water vapor which can initiate corrosion.

Device and method for improving corrosion resistance and etch tool

An integrated circuit 10 has a programmable Zener diode with diffusion regions 18 and 16 and metal contacts 34 and 32. A barrier metal 30 is disposed between one contact 32 and the substrate 12; another contact region 18 has no barrier metal on its surface. A polysilicon layer 22 is self-aligned with surface regions 18 and diffusion region 18. A silicide layer 128 may be used on the polysilicon layer 22 and on surface region 18.

Programmable element in barrier metal device

Growing community of inventors

Palm Bay, FL, United States of America

John J Hackenberg