Intel Corporation

John J Beatty

Hemanth K Dhavaleswarapu

Johanna M Swan

Feras Eid

Sergio Antonio Chan Arguedas

Jason A Garcia

Dinesh P R Thanu

Nachiket R Raravikar

Syadwad Jain

Suzana Prstic

Dinesh Padmanabhan Ramalekshmi Thanu

Peng T Li

Pramod Malatkar

Vipul V Mehta

Nicholas Holmberg

Arnab Choudhury

Shenavia S Howell

Marco Aurelio Cartas Ayala

Raymond A Krick

Sachin Deshmukh

Prakriti Choudhary

Luke J Garner

Venkata Suresh Guthikonda

Yonghao An

A device package and a method of forming a device package are described. The device package has dies disposed on a substrate, and one or more layers with a high thermal conductivity, referred to as the highly-conductive (HC) intermediate layers, disposed on the dies on the substrate. The device package further includes a lid with legs on an outer periphery of the lid, a top surface, and a bottom surface. The legs of the lid are attached to the substrate with a sealant. The bottom surface of the lid is disposed over the one or more HC intermediate layers and the one or more dies on the substrate. The device package may also include thermal interface materials (TIMs) disposed on the HC intermediate layers. The TIMs may be disposed between the bottom surface of the lid and one or more top surfaces of the HC intermediate layers.

Package with a highly conductive layer deposited on die using throughput additive deposition prior to TIM1 dispense

Semiconductor packages having a sealant bridge between an integrated heat spreader and a package substrate are described. In an embodiment, a semiconductor package includes a sealant bridge anchoring the integrated heat spreader to the package substrate at locations within an overhang gap laterally between a semiconductor die and a sidewall of the integrated heat spreader. The sealant bridge extends between a top wall of the integrated heat spreader and a die side component, such as a functional electronic component or a non-functional component, or a satellite chip on the package substrate. The sealant bridge modulates warpage or stress in thermal interface material joints to reduce thermal degradation of the semiconductor package.

Semiconductor package having sealant bridge

A microelectronic package may be fabricated to include a microelectronic substrate, at least one microelectronic device attached to the microelectronic substrate, a heat dissipation device in thermal contact with at least one microelectronic device and having at least one projection attached to the microelectronic substrate, and at least one standoff extending from the at least one projection, wherein the at least one standoff contacts the microelectronic substrate to control the bond line thickness between the heat dissipation device and at least one microelectronic device and/or to control the bond line thickness of a sealant which may be used to attached the at least one projection to the microelectronic substrate.

Heat spreader edge standoffs for managing bondline thickness in microelectronic packages

Embodiments may relate to a microelectronic package that includes a die and a backside metallization (BSM) layer positioned on the face of the die. The BSM layer may include a feature that indicates that the BSM layer was formed on the face of the die by a masked deposition technique. Other embodiments may be described or claimed.

Package-level backside metallization (BSM)

A device package and a method of forming a device package are described. The device package includes a plurality of posts disposed on a substrate. Each post has a top surface and a bottom surface that is opposite from the top surface. The device package also has one or more dies disposed on the substrate. The dies are adjacent to the plurality of posts on the substrate. The device package further includes a lid disposed above the plurality of posts and the one or more dies on the substrate. The lid has a top surface and a bottom surface that is opposite from the top surface. Lastly, an adhesive layer attaches the top surfaces of the plurality of posts and the bottom surface of the lid. The device package may also include one or more thermal interface materials (TIMs) disposed on the dies.

Substrate integrated posts and heat spreader customization for enhanced package thermomechanics

A microelectronic package may be fabricated to include a microelectronic substrate, a plurality of microelectronic devices attached to the microelectronic substrate, a heat dissipation device in thermal contact with at least one of the plurality of microelectronic devices and attached to the microelectronic substrate, and at least one offset spacer attached between the microelectronic substrate and the heat dissipation device to control the bondline thickness between the heat dissipation device and at least one of the plurality of microelectronic devices.

Standoff spacers for managing bondline thickness in microelectronic packages

A semiconductor package includes a semiconductor die arranged on a substrate. The semiconductor package includes a stiffener structure arranged on the substrate. The stiffener structure is spaced at a distance from the semiconductor die. The stiffener structure includes a molding compound material.

Semiconductor package, and a method for forming a semiconductor package

Methods, systems, and apparatuses that assist with cooling semiconductor packages, such as multi-chip packages (MCPs) are described. A semiconductor package includes a component on a substrate. The component can include one or more semiconductor dies. The package can also include a multi-reference integrated heat spreader (IHS) solution (also referred to as a smart IHS solution), where the smart IHS solution includes a smart IHS lid. The smart IHS lid includes a cavity formed in a central region of the smart lid. The smart IHS lid can be on the component, such that the cavity corresponds to the component. A first thermal interface material layer (TIM-layer 1) can be on the component. An individual IHS lid (IHS slug) can be on the TIM-layer 1. The IHS slug can be inserted into the cavity. Furthermore, an intermediate thermal interface material layer (TIM-1A layer) can be between the IHS slug and the cavity.

Multi-reference integrated heat spreader (IHS) solution

A method of manufacturing a plurality of electronic devices is provided. Each one of a plurality of first conductive terminals on a plurality of integrated circuits formed on a device wafer is connected to a respective one of a plurality of second conductive terminals on a carrier wafer, thereby forming a combination wafer assembly. The combination wafer assembly is singulated between the integrated circuits to form separate electronic assemblies. The combination wafer assembly also allows for an underfill material to be introduced and to cured at wafer level and for thinning of the device wafer at wafer level without requiring a separate supporting substrate. Alignment between the device wafer and the carrier wafer can be tested by conducting a current through first and second conductors in the device and carrier wafers, respectively.

Method of manufacturing a plurality of electronic assemblies

According to one aspect of the invention, an electronic assembly is provided. The electronic assembly includes a first substrate having an integrated circuit formed therein and a second substrate. The first and second substrates are interconnected by a plurality of bi-material interconnects that are electrically connected to the integrated circuit and have a first component comprising a conductive first material with a first coefficient of thermal expansion and a second component comprising a second material with a second coefficient of thermal expansion. The first and second components are connected and shaped such that when the temperature of the bi-material interconnects changes the interconnects each bend towards the first or second component. When the temperature of the second substrate increases, the second substrate expands away from a central portion thereof. The bi-material interconnects are arranged such that the bi-material interconnects bend away from the central portion of the second substrate.

Method of making an electronic assembly

Electronic assembly having multi-material interconnects

In some embodiments, a retractable ledge socket is presented. In this regard, a socket ledge is introduced to receive a processor, and to reposition to allow the processor to contact socket connections. Other embodiments are also disclosed and claimed.

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Chandler, AZ, United States of America

John J Beatty