International Business Machines Corporation

John Harold Magerlein

Evan G Colgan

Richard Paul Volant

Kevin Shawn Petrarca

John Michael Cotte

Raschid Jose Bezama

John Ulrich Knickerbocker

Roger R Schmidt

Sampath Purushothaman

Hariklia Deligianni

George Frederick Walker

Carlos Juan Sambucetti

Panayotis Constantinou Andricacos

Kenneth Jay Stein

Chirag Suryakant Patel

Christopher Vincent Jahnes

Kenneth Charles Marston

Daniel C Edelstein

Michael A Gaynes

Edmund Juris Sprogis

Xiaojin Wei

Herbert I Stoller

Madhusudan K Iyengar

Duixian Liu

Jeffrey Allen Zitz

Brian Paul Gaucher

Mahadevaiyer Krishnan

Cornelia Kang-I Tsang

Sherif Ahmed Goma

Ullrich Richard Pfeiffer

Jennifer L Lund

James Anthony Tornello

Nils Deneke Hoivik

L Paivikki Buchwalter

Janusz Grzyb

Paul William Coteus

Paul Stephen Andry

Gareth Geoffrey Hougham

John G Torok

Thomas J Brunschwiler

Kamal Kumar Sikka

Hilton T Toy

Robert L Wisnieff

Alan Frederic Benner

Bruce Kenneth Furman

Frank Louis Pompeo

How Tzu Lin

Subhash Laxman Shinde

Maheswaran Surendra

Amilcar R Arvelo

Hubert Harrer

Yu-Ting Cheng

Daniel J Stigliani, Jr

Jamil A Wakil

Albert E Ruehli

Samuel McKnight

Kathryn C Rivera

George Liang-Tai Chiu

Joseph J Van Horn

Simon M Karecki

Paivikki Buchwalter

James Tornello

Panayotis Andricacos

Semiconductor package structures are provided which are designed to have liquid coolers integrally packaged with first level chip modules. In particular, apparatus for integrally packaging a liquid cooler device within a first level chip package structure include structures in which a liquid cooler device is thermally coupled directly to the back side of an integrated circuit chip flip-chip mounted on flexible chip carrier substrate. The liquid cooler device is mechanically coupled to the package substrate through a metallic stiffener structure that is bonded to the flexible package substrate to provide mechanical rigidity to the flexible package substrate.

Semiconductor package structures having liquid cooler integrated with first level chip package modules

A chip package includes: a substrate; a plurality of conductive connections in contact with the silicon carrier; a silicon carrier in a prefabricated shape disposed above the substrate, the silicon carrier including: a plurality of through silicon vias for providing interconnections through the silicon carrier to the chip stack; liquid microchannels for cooling; a liquid coolant flowing through the microchannels; and an interconnect to one or more chip stacks. The chip package further includes a cooling lid disposed above the chip stack providing additional cooling.

Silicon based microchannel cooling and electrical package

A cooler having a unitary construction including a channel portion including a plurality of fins on a base, the plurality of fins defining a plurality of microchannels therebetween, a tapered opening formed in a set of the plurality of fins, a manifold portion disposed on an edge portion of the base, the manifold portion including an inlet port and an outlet port disposed above the tapered opening in the plurality of fins, and a separator sheet including at least two elongated openings disposed between the channel portion and the manifold portion.

Structure and apparatus for cooling integrated circuits using copper microchannels

A chip package includes: a substrate; a plurality of conductive connections in contact with the silicon carrier; a silicon carrier in a prefabricated shape disposed above the substrate, the silicon carrier including: a plurality of through silicon vias for providing interconnections through the silicon carrier to the chip; liquid microchannels for cooling; a liquid coolant flowing through the microchannels; and an interconnect to one or more chips or chip stacks.

A cooler includes a base layer, a cooling layer including at least one inlet slot and at least one outlet slot for flowing a coolant across a cooling structure including a plurality of staggered fins arranged in rows and columns, wherein fins of adjacent columns are staggered, and at least one manifold layer disposed on the cooling layer for flowing the coolant from a cooler inlet to the at least inlet slot and from the at least one outlet slot to a cooler outlet, the at least one manifold layer having a top layer comprising the cooler inlet and the cooler outlet.

Stacked and redundant chip coolers

Structure and apparatus for cooling integrated circuits using cooper microchannels

Semiconductor package structures having liquid coolers integrated with first level chip package modules

A Silicon Based Package (SBP) is formed starting with a thick wafer, which serves as the base for the SBP, composed of silicon which has a first surface and a reverse surface which are planar. Then form an interconnection structure including metal capture structures in contact with the first surface and multilayer conductor patterns over the first surface. Form a temporary bond between the SBP and a wafer holder, with the wafer holder being a rigid structure. Thin the reverse side of the wafer to a desired thickness to form an Ultra Thin Silicon Wafer (UTSW) for the SBP. Form via holes with tapered or vertical sidewalls, which extend through the UTSW to reach the metal capture structures. Then form metal pads in the via holes which extend through the UTSW, making electrical contact to the metal capture structures. Then bond the metal pads in the via holes to pads of a carrier.

Method and manufacture of silicon based package and devices manufactured thereby

A plurality of heat-dissipating electronic chips are arranged in a vertical chip stack. The electronic chips have electronic components thereon. A cold plate is secured to a back side of the chip stack. A silicon carrier sandwich, defining a fluid cavity, is secured to a front side of the chip stack. An inlet manifold is configured to supply cooling fluid to the cold plate and the fluid cavity of the silicon carrier sandwich. An outlet manifold is configured to receive the cooling fluid from the cold plate and the fluid cavity of the silicon carrier sandwich. The cold plate, the silicon carrier sandwich, the inlet manifold, and the outlet manifold are configured and dimensioned to electrically isolate the cooling fluid from the electronic components. A method of operating an electronic apparatus and a method of manufacturing an electronic apparatus are also disclosed. Single-sided heat removal with double-sided electrical input-output and double-sided heat removal with double-sided electrical input-output are also disclosed.

Double-face heat removal of vertically integrated chip-stacks utilizing combined symmetric silicon carrier fluid cavity and micro-channel cold plate

An apparatus to reduce a thermal penalty of a three-dimensional (3D) die stack for use in a computing environment is provided and includes a substrate installed within the computing environment, a first component to perform operations of the computing environment, which is coupled to the substrate in a stacking direction, a set of second components to perform operations of the computing environment, each of which is coupled to the first component and segmented with respect to one another to form a vacated region, a thermal interface material (TIM) disposed on exposed surfaces of the first and second components, and a lid, including a protrusion, coupled to the substrate to overlay the first and second components such that the protrusion extends into the vacated region and such that surfaces of the lid and the protrusion thermally communicate with the first and second components via the TIM.

Segmentation of a die stack for 3D packaging thermal management

The invention is the technology of providing a packaging intermediate product that can serve as an interface substrate that is to be positioned between different circuitry types where the dimensions are approaching the sub 100 micrometer range. The invention involves a dielectric wafer structure where the first and second area surfaces of the wafer are separated by a distance that is of the order of the electrical via design length, and an array of spaced vias through the wafer arranged with each via filled with metal surrounded by a chemical metal deposition promoting layer with each via terminating flush with a wafer surface. The wafer structure is achieved by forming an array of blind via openings through the first surface of the dielectric wafer to a depth approaching the via design length, lining the walls for adhesion enhancement, filling the blind via openings completely with a chemically deposited metal, removing material at the first wafer surface thereby planarizing the filled vias, and removing material at the second wafer surface thereby exposing the vias at the design length.

Technology for fabrication of packaging interface substrate wafers with fully metallized vias through the substrate wafer

Silicon based package

A method of forming an inductor. The method including: (a) forming a dielectric layer on a top surface of a substrate; after (a), (b) forming a lower trench in the dielectric layer; after (b), (c) forming a resist layer on a top surface of the dielectric layer; after (c), (d) forming an upper trench in the resist layer, the upper trench aligned to the lower trench, a bottom of the upper trench open to the lower trench; and after (d), (e) completely filling the lower trench and at least partially filling the upper trench with a conductor in order to form the inductor.

Method of fabricating a high Q factor integrated circuit inductor

Apparatus and methods are provided for packaging multi-chip modules with liquid cooling modules designed to provide different thermal resistances for effectively conducting heat from various chips with disparate cooling requirements while minimizing mechanical stresses in thermal bonds due to thermal excursions.

Apparatus and methods for high-performance liquid cooling of multiple chips with disparate cooling requirements

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Yorktown Heights, NY, United States of America

John Harold Magerlein