Other

Micro Power Systems, Inc.

Linear Integrated Systems, Inc.

John H Hall

J Kirkwood Rough

Walter Finkelstein

Omer Kal

An integrated transistor device operates with a linear triode vacuum tube like characteristic with a very low output impedance and a large interaction between the gate and drain potentials. The drain current of a first transistor is connected directly to the source of a second transistor which has a low input impedance matching the output impedance of the first transistor. The gate of the second transistor is held at a positive potential and functions to provide isolation of the varying drain signal from the drain of the first transistor and to provide a high impedance at the output terminal. This device structure provides high input impedance, high current gain, high output impedance and a linear operating characteristic.

Intergrated field effect transistor device for high power and voltage

Disclosed is an integrated transistor structure having increased conductance and operating speed including a complementary insulated gate field effect transistor pair, each including a source and a drain region with a gate contact positioned therebetween, ohmic contacts to the sources, and a rectifying junction contact to each of the drain regions. The gates of the two transistors are interconnected and function as the input terminal, and the two rectifying contacts are interconnected as the output of the device. The structure includes a semiconductor substrate having slow diffusant dopants therein or implanted metal ions of cobalt, molybdenum, or tungsten. The structure further includes an epitaxial semiconductor layer with resistance on the order of 0.5 to 1.0 ohm cm and a thickness of 1.5 to 5.0 .mu.m. The device regions for the field effect transistor pair are formed in the epitaxial semiconductor layer. Current from a positive voltage source is applied through the substrate to the source of a P-channel field effect transistor, thereby reducing switch back effect.

Compound modulated integrated transistor structure with reduced bipolar

An array of electrodes for use in a flat panel display includes a plurality of electron emitters formed of polycrystalline or single crystalline silicon which has been selectively etched to form pores in the emitters. The electrode array is then electroplated in a methane plasma to deposit a carbon compound such as silicon carbide on the surfaces of the emitters and in the pores of the emitters. Each emitter has a generally flat electron emitting surface which facilitates a longer life for the electrode array, the porous structure of the emitters increasing the electron emission efficiency of the emitters in relatively low electric fields. The electrode array can be integral with a support substrate by anisotropically etching the substrate to form the emitters. A layered interconnect structure can be formed on a surface of the silicon substrate for providing the interconnect structure for the electrode array.

Flat panel display having improved electrode array

A contact and interconnect structure for a semiconductor integrated circuit includes a thin layer of refractory metal on a contact surface of the substrate through an opening in an overlying insulation layer with boron ions implanted into the substrate through the layer of refractory metal and the contact surface to ensure a uniform ohmic contact. An interconnect structure is then formed on the insulation layer and on the thin layer of refractory metal including a first layer of a refractory metal nitride on the insulation layer, a second layer of refractory metal on the first layer of refractory metal nitride, and a second layer of refractory metal nitride on the second layer of refractory metal.

High temperature refractory metal contact in silicon integrated circuits

Disclosed is an integrated transistor structure having increased conductance and operating speed including a complementary insulated gate field-effect transistor pair, each including a source and drain region with a gate contact positioned therebetween, ohmic contacts to the source and drain regions, and a p-n junction contact to each of the drain regions. The gates of the two transistors are interconnected and function as the input terminal, and the two p-n junction contacts are interconnected as the output of the device. The operation of the device is such that the lightly-doped drain regions act as bases of bipolar transistors, with the emitters formed by the p-n junction diodes. Minority carriers injected by the diodes modulate the channel regions, thereby lowering their resistivity and increasing the transconductance of the device without increasing the physical size or the capacitance of the device and thereby improving the speed of the device. Second p-n junction contacts to the drain regions are interconnected, and form auxiliary bipolar transistors in the drain regions to extract charge stored in the main transistor collector to base junction and increasing switching speed in the turn off direction. In turn on, the second p-n junction holds the base away from ground thereby increasing turn on speed.

Low voltage compound modulated integrated transistor structure

An interconnect for an integrated circuit in a semiconductor substrate formed on an insulation layer on a surface of the substrate includes a first layer of a refractory metal nitride on said insulation layer, a layer of refractory metal on said first layer of refractory metal nitride, and a second layer of refractory metal nitride on said Layer of refractory metal, said first layer of refractory metal layer nitride, said layer of refractory metal, and said second layer of refractory metal nitride forming said interconnect structure. The interconnect structure makes contact with the integrated circuit through openings in the insulation layer. Boron ions are implanted into the substrate through the interconnect structure in the openings to facilitate ohmic contact between the substrate and the interconnect structure.

Method of fabricating high temperature refractory metal nitride contact

Disclosed is an integrated transistor structure having increased conductance and operating speed including a complementary insulated gate field-effect transistor pair, each transistor including a source region and a drain region with a gate contact positioned over a channel region therebetween, an ohmic contact to the source regions, and a Schottky contact or PN rectifying junction to each of the drain regions. The dopant concentration of the drain regions is sufficiently low to prevent the Schottky contacts from forming ohmic contacts with the drain regions. The gates of the two transistors are interconnected and function as the input terminal, and the two Schottky contacts are interconnected as the output of the device. The operation of the device is such that the lightly doped drain regions act as bases of bipolar transistors, with the emitters formed by the Schottky and PN diodes. Majority carriers injected by the Schottky diodes modulate the channel regions, thereby lowering their resistivity and increasing the transconductance of the device without increasing the physical size or the capacitance of the device and thereby improving the speed of the device. Speed of operation in enhanced by providing dielectric material between the drain regions and the substrate.

Conductance modulated integrated transistor structure with low drain

Disclosed is an integrated transistor structure having increased conductance and operating speed including a complementary insulated gate field-effect transistor pair, each transistor including a source region and drain region with a gate contact positioned therebetween, ohmic contacts to the source and drain regions, and a diode junction contact to each of the drain regions. The gates of the two transistors are interconnected and function as the input terminal, and the two diode junction contacts are interconnected as the output of the device. The operation of the device is such that the lightly-doped drain regions act as bases of bipolar transistors, with the emitters formed by the p-n junction diodes. The transconductors of the MOS transistors is multiplied by the beta of the bipolar transistors. The ohmic contacts to the drain regions can be interconnected, and the low on resistance of the opposite polarity drive transistor extracts any excess stored charge in the drain region. Two clocked transistors interconnect the complementary insulated gate field-effect transistor pair to voltage potentials whereby operation of the integrated transistor structure is clocked.

Clocked CBICMOS integrated transistor structure

This is an invention for a complementary transistor pair which includes an n-channel double-diffused-metal-oxide-semiconductor transistor having a source, a drain and an insulated gate. A Schottky barrier junction diode is formed to the drain of the n-channel transistor. The transistor pair also includes a p-channel double-diffused-metal-oxide-semiconductor transistor which also has a source, a drain and an insulated gate. A second Schottky barrier junction diode is formed to the drain of the p-channel transistor. The two Schottky diodes are electrically coupled to one another.

Double diffused CMOS with Schottky to drain contacts

A CBiCMOS transmission gate in which the sources of a CMOS transistor pair are connected to an input and the drains are connected to the bases of a complementary bipolar transistor pair. The bipolar transistor pair is serially connected between a plus voltage potential and ground whereby a logic one applied to the input is transmitted through the PMOS transistor to the base of an NPN transistor which applies the plus voltage to an output terminal, and a logic zero applied to the input is transmitted to the NMOS transistor to the base of a PNP transistor to apply ground to the output terminal.

Complementary bipolar complementary CMOS (CBiCMOS) transmission gate

Disclosed is an integrated transistor structure having increased conductance and operating speed including a complementary insulated gate field-effect transistor pair, each including a source and drain region with a gate contact positioned therebetween, ohmic contacts to the source and drain regions, and a p-n junction contact to each of the drain regions. The gates of the two transistors are interconnected and function as the input terminal, and the two p-n junction contacts are interconnected as the output of the device. The operation of the device is such that the lightly-doped drain regions act as bases of bipolar transistors, with the emitters formed by the p-n junction diodes. Minority carriers injected by the diodes modulate the channel regions, thereby lowering their resistivity and increasing the transconductance of the device without increasing the physical size or the capacitance of the device and thereby improving the speed of the device. The ohmic contacts to the drain regions are interconnected, and the low on resistance of the opposite polarity drive transistor extracts any excess stored charge in the drain region.

Compound modulated integrated transistor structure

Disclosed is an integrated transistor structure having increased conductance and operating speed including a complementary insulated gate field-effect transistor pair, each including a source and drain region with a gate contact positioned therebetween, an ohmic contact to the source regions, and a Schottky contact to each of the drain regions. The dopant concentration of the drain regions is sufficiently low to prevent the Schottky contact from forming an ohmic contact with the drain regions. The gates of the two transistors are interconnected and function as the input terminal, and the two Schottky contacts are interconnected as the output of the device. The operation of the device is such that the lightly-doped drain regions act as bases of bipolar transistors, with the emitters formed by the Schottky diodes. Minority and majority carriers injected by the Schottky diodes modulate the channel regions, thereby lowering their resistivity and increasing the transconductance of the device without increasing the physical size or the capacitance of the device and thereby improving the speed of the device.

Conductance-modulated integrated transistor structure

A CMOS analog to digital flash converter cell includes an input for receiving an analog signal to be converted to a digital value, a predetermined connection to a resistance ladder for providing a reference voltage, an output, CMOS comparator/inverter stage having drain connections commonly connected to the output, a level shift capacitor connected to input gate connections of the comparator/inverter stage, and three bi-phase clocked CMOS switches: a first switch for connecting the reference voltage to one side of the level shift capacitor during a first phase of a clock period; a second switch for connecting the output to the input gate connections on the other side of the level shift capacitor during the first phase of the clock period, and a third switch for connecting the input voltage to the one side of the level shift capacitor during a second phase of the clock period. The new input circuit includes a first bipolar transistor having a base connection to the predetermined resistance ladder connection and having an output node connected to the first CMOS switch and a second bipolar transistor having a base connection connected to the input and having an output node connected to the third CMOS switch.

Bipolar input circuit for CMOS flash analog to digital converter

An integrated circuit structure for isolating circuit structures in closely packed integrated circuits, and a method for making the same. The isolation structure includes a semiconductor body having a surface, an insulatory layer on the surface having an aperture and an offset adjacent to the aperture, the aperture and offset being filled with epitaxial semiconductor material, at least a portion of the epitaxial material being single crystal semiconductor, said structure being used for the fabrication of standard semiconductor devices. The method uses conventional processing techniques that require a minimum of additional cost over prior art, and yet provide a high degree of device isolation and density.

Method of forming localized epitaxy and devices formed therein

A semiconductor structure including a body of semiconductor material with selected surface areas of at least one surface of said body of semiconductor material including an oxide layer containing impurities characterizing a predetermined conductivity type, an inset region of said predetermined conductivity type under each of said areas formed by diffusion of impurities from said oxide layer and a silicon nitride layer covering said predetermined oxide areas and the remaining surface areas of said at least one surface of said body of semiconductor material. The method of forming inset regions of predetermined conductivity type in a body of semiconductor material which includes the steps of forming on predetermined areas of a surface of said body a doped oxide layer, forming a silicon nitride layer on said surface to cover said areas and the remainder of the surface of said body and heating said body to cause the impurities in said oxide layer to diffuse inwardly into the body to form inset regions under said areas while said silicon nitride layer prevents out-gasing of impurities from the oxide areas.

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San Jose, CA, United States of America

John H Hall