International Business Machines Corporation

Dongbu Electronics, Co. Ltd.

Jeol Usa, Inc.

John Gerard Gaudiello

Kangguo Cheng

Juntao Li

Daniel C Edelstein

Carlos Juan Sambucetti

Gerald L Ballard

David V Horak

Toshiharu Furukawa

Mark Charles Hakey

Charles W Koburger, Iii

Steven J Holmes

Sandra Guy Malhotra

George Frederick Walker

Yun-Yu Wang

Judith Marie Rubino

Jack Allan Mandelman

William R Tonti

Voya Rista Markovich

Timothy Joseph Dalton

Eugene John O'Sullivan

Luis Jesus Matienzo

Mahadevaiyer Krishnan

James J Demarest

Ethan Harrison Cannon

Anthony Gene Domenicucci

Maurice McGlashan-Powell

Horatio Seymour Wildman

Liying Jiang

Steven H Boettcher

Robert Douglas Edwards

Lawrence Richard Cutting

Nikhil Mohan Murdeshwar

Leon J Kimball

Cyryl Cabral, Jr

Chung H Lam

Panayotis Constantinou Andricacos

John Joseph Konrad

Ashwinkumar C Bhatt

Michael Abramovich Gribelyuk

John Bruley

Ronald Dean Goldblatt

Timothy Leroy Wells

James D Herard

Jeffrey McKeveny

James Edward Fluegel

Milan Paunovic

Keith E Barton

Thomas A Bauer

Masahiro Kawasaki

Charles William Koburger Iii

Jeffrey S McMurray

David Vaclav Horak

Steven John Holmes

William Robert Tonti

Ethan Harrison c/o Ibm United Kingdom Ltd Intellectual Property Law Cannon

A method of forming a logic device and a power device on a substrate is provided. The method includes forming a first vertical fin on a first region of the substrate and a second vertical fin on a second region of the substrate, wherein an isolation region separates the first region from the second region, forming a dielectric under-layer segment on the second vertical fin on the second region, and forming a first gate structure on the dielectric under-layer segment and second vertical fin on the second region.

Fabrication of logic devices and power devices on the same substrate

A method for manufacturing a semiconductor device includes growing a first strained semiconductor layer on a substrate, the first strained semiconductor layer having a first type of strain, wherein the substrate comprises a first crystalline orientation at a top surface of the substrate, forming at least one trench in the substrate, wherein exposed sidewalls of the at least one trench have a second crystalline orientation different from the first crystalline orientation, growing a buffer layer in the at least one trench from the exposed sidewalls of the trench, and growing a second strained semiconductor layer on the buffer layer, the second strained semiconductor layer having a second type of strain, wherein the first type of strain is different from the second type of strain.

Forming strained channels for CMOS device fabrication

Method and structure of forming strained channels for CMOS device fabrication

A semiconductor device and process of making the same generally includes simultaneously forming nanosheet capacitors with nanosheet FET devices on the same substrate. The nanosheets in the capacitor have a width and are coupled to one another by sacrificial layers, wherein the sacrificial layers have a width smaller than the nanosheet width, and wherein the nanosheets and the sacrificial layers are conductively coupled to the substrate. The nanosheets in the FET devices are spaced apart and free of sacrificial layers. The nanosheets in the FET device have a width less than half the width of the nanosheets in the capacitor region.

Integrated capacitors with nanosheet transistors

A memory cell in an integrated circuit is fabricated in part by forming a lower electrode feature, an island, a sacrificial feature, a gate feature, and a phase change feature. The island is formed on the lower electrode feature and has one or more sidewalls. It comprises a lower doped feature, a middle doped feature formed above the lower doped feature, and an upper doped feature formed above the middle doped feature. The sacrificial feature is formed above the island, while the gate feature is formed along each sidewall of the island. The gate feature overlies at least a portion of the middle doped feature of the island and is operative to control an electrical resistance therein. Finally, the phase feature is formed above the island at least in part by replacing at least a portion of the sacrificial feature with a phase change material. The phase change material is operative to switch between lower and higher electrical resistance states in response to an application of an electrical signal.

Phase change memory cell with vertical transistor

Design structure embodied in a machine readable medium for designing, manufacturing, or testing a design in which the design structure includes devices formed in a hybrid substrate characterized by semiconductor islands of different crystal orientations. An insulating layer divides the islands of at least one of the different crystal orientations into mutually aligned device and body regions. The body regions may be electrically floating relative to the device regions.

Design structure incorporating a hybrid substrate

A method for simultaneously forming multiple line-widths, one of which is less than that achievable employing conventional lithographic techniques. The method includes providing a structure which includes a memory layer and a sidewall image transfer (SIT) layer on top of the memory layer. Then, the SIT layer is patterned resulting in a SIT region. Then, the SIT region is used as a blocking mask during directional etching of the memory layer resulting in a first memory region. Then, a side wall of the SIT region is retreated a retreating distance D in a reference direction resulting in a SIT portion. Said patterning comprises a lithographic process. The retreating distance D is less than a critical dimension CD associated with the lithographic process. The SIT region includes a first dimension Wand a second dimension Win the reference direction, wherein CD&#x3c;W&#x3c;2D&#x3c;W

Sidewall image transfer processes for forming multiple line-widths

Hybrid substrates characterized by semiconductor islands of different crystal orientations and methods of forming such hybrid substrates. The methods involve using a SIMOX process to form an insulating layer. The insulating layer may divide the islands of at least one of the different crystal orientations into mutually aligned device and body regions. The body regions may be electrically floating relative to the device regions.

Hybrid substrates and methods for forming such hybrid substrates

A high quality electron microscopy sample suitable for electron holography is prepared by forming markers filled with TEOS oxide and by repeatedly applying multiple coats of an adhesive followed by a relatively low temperature cure after each application. The TEOS oxide marker is readily visible during the polish, has a similar polish rate as a semiconductor material, and reduces contamination during sample preparation. The repeated application of adhesives separated by relatively low temperature cures increases the adhesive strength of the adhesive material to the semiconductor material without making it too brittle. This results in an improved control and yield of the sample preparation process.

Method of TEM sample preparation for electron holography for semiconductor devices

A method for preparing a transmission electron microscopy (TEM) sample for electron holography includes forming a sacrificial material over an area of interest on the sample, and polishing the sample to a desired thickness, wherein the area of interest is protected from rounding during the polishing. The sacrificial material is removed from the sample following the polishing.

Transmission electron microscopy sample preparation method for electron holography

An inline electron holograph method for observing a specimen with a transmission electron microscope having an electron gun, a collimating lens system, two spaced objective lenses, a biprism, and an imaging means comprises the steps of: with the first objective lens forming a virtual image of a portion of the specimen; with the second objective lens focussing the virtual image at an intermediate image plane to form an intermediate image; and projecting the intermediate image onto the imaging means.

Electron holography method

A process for manufacturing a land grid array connector for a printed wiring board is disclosed. The process does not require electroplating precious metal overlays. Therefore, no commoning bar is required. Another benefit of the invention includes a connector design using only a flash, soft gold application in the outer surface of the connector. Physical hardness and durability are derived from a thin palladium layer lying beneath the flash gold layer.

Process for manufacturing a printed wiring board

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Poughkeepsie, NY, United States of America

John Gerard Gaudiello