Intel Corporation

Other

Intel Corporationd

John G Meyers

Florence R Pon

Bilal Khalaf

Yong She

Bin Liu

Hyoung Il Kim

Richard Patten

Zhicheng Ding

Min-Tih Ted Lai

Yuhong Cai

Brian J Long

Sireesha Gogineni

Juan E Dominguez

Steven R Eskildsen

Richard B Foehringer

Mao Guo

Jason Snodgress

Leo J Craft

Lingyan L Tan

An electronic assembly includes a plurality of electronic die arranged into shingles, each shingle having a multiple offset stacked die coupled by cascading connections. Each shingle is arranged in a stack of shingles with alternate shingles having die stacked in opposite directions and offset in a zigzag manner to facilitate vertical electrical connections from a top of the electronic assembly to a bottom die of each shingle.

Die stack with cascade and vertical connections

A packaged device () includes a substrate () and one or more contacts () disposed on a side of the substrate (). Structures of the packaged device () define at least in part a recess region () that extends from the side of the substrate () and through the substrate (), where one or more contacts () of a second hardware interface are disposed in the recess region (). The one or more contacts () of the first hardware interface enable connection of the packaged device () to a printed circuit board. The one or more contacts () of the second hardware interface enable connection between one or more IC dies of the packaged device () and another IC die () that is a component of the packaged device () or of a different packaged device.

Packaged integrated circuit device with recess structure

Embodiments include systems in packages (SiPs) and a method of forming the SiPs. A SiP includes a package substrate and a first modularized sub-package over the package substrate, where the first modularized sub-package includes a plurality of electrical components, a first mold layer, and a redistribution layer. The SiP also includes a stack of dies over the package substrate, where the first modularized sub-package is disposed between the stack of dies. The SiP further includes a plurality of interconnects coupled to the stack of dies, the first modularized sub-package, and the package substrate, wherein the redistribution layer of the first modularized sub-package couples the stack of dies to the package substrate with the plurality of interconnects. The SiP may enable the redistribution layer of the first modularized sub-package to couple the electrical components to the stacked dies and the package substrate without a solder interconnect.

System in package with interconnected modules

Electronic device package technology is disclosed. An electronic device package in accordance with the present disclosure can include a substrate, a plurality of electronic components in a stacked relationship, and an encapsulant material encapsulating the electronic components. Each of the electronic components can be electrically coupled to the substrate via a wire bond connection and spaced apart from an adjacent electronic component to provide clearance for the wire bond connection. The encapsulant can be disposed between center portions of adjacent electronic components. Associated systems and methods are also disclosed.

Electronic device package

A microelectronic package may be fabricated having at least one microelectronic die attached to a microelectronic substrate, wherein the microelectronic substrate includes at least one notch formed in at least one side thereof. The microelectronic dice may be attached to a first surface of the microelectronic substrate and in electronic communication with a bond pad on a second surface of the microelectronic substrate with a bond wire which extends through the notch in the microelectronic substrate.

Microelectronic structures having notched microelectronic substrates

A high density die package configuration is shown for use on system boards. In one example, an apparatus includes a system board, a first package mounted to the system board, a second package mounted to the system board, and an interface package mounted between the first and the second package and coupled directly to the first package and to the second package through the respective first and second packages.

High density die package configuration on system boards

A data storage system is described that uses wafer-level packaging. In one embodiment an apparatus includes a silicon wafer, a plurality of memory cells formed directly on the wafer, an encapsulant formed over the memory cells, a plurality of wiring connections to connect the memory cells to an external interface, a memory controller, and an external interface.

Data storage system using wafer-level packaging

Techniques and mechanisms for interconnecting stacked integrated circuit (IC) dies. In an embodiment, a first end of a wire is coupled to a first IC die of a stack, where a second end of the wire is further anchored to the stack independent of the coupled first end. A package material is subsequently disposed around IC dies of the stack and a first portion of the wire that includes the first end. Two-point anchoring of the wire to the stack aids in providing mechanical support to resist movement that might otherwise displace and/or deform the wire while the package material is deposited. In another embodiment, the first portion of the wire is separated from the rest of the wire, and a redistribution layer is coupled to the first portion to enable interconnection between the first IC die and another IC die of the stack.

Method, apparatus and system to interconnect packaged integrated circuit dies

A system in package and method of making as system in package are disclosed. The system in package has a substrate () with a plurality of passive devices () mounted thereon. A molding compound () envelopes the plurality of passive devices () to define a flat surface () substantially parallel to a surface of the substrate (). A plurality of integrated circuit dies () is coupled successively to the flat surface ().

Pre-molded active IC of passive components to miniaturize system in package

Techniques and mechanisms to facilitate connection with one or more integrated circuit (IC) dies of a packaged device. In an embodiment, the packaged device includes a first substrate coupled to a first side of a package, and a second substrate coupled to a second side of the package opposite the first side. Circuitry, coupled via the first substrate to one or more IC dies disposed in the package, includes a circuit structure disposed at a cantilever portion of the first substrate. The cantilever portion extends past one or both of an edge of the first side and an edge of the second side. In another embodiment, a hardware interface disposed on the second substrate enables coupling of the packaged device to another device.

Packaged integrated circuit device with cantilever structure

A method includes populating a circuit board with components, and encapsulating the circuit board and the components with a material. The method further includes separating the circuit board into a plurality of separate devices.

Packaging method for circuit board

A process and apparatus for packaging a tape substrate are provided. A first chip is encapsulated to a first side of a tape substrate to form a first capsule in a first segment of the tape substrate. The first segment of the tape substrate is secured to a first clamping element. A second segment of the tape substrate adjacent the first segment is secured to a second clamping element. At least one of the first segment and the second segment is moved to stack the second segment over the first capsule. The first clamping element and second clamping element can move independently of each other.

Growing community of inventors

Sacramento, CA, United States of America

John G Meyers