Unity Semiconductor Corporation

Advanced Micro Devices Corporation

Hefei Reliance Memory Limited

Amazon Technologies, Inc.

John Espinoza Sanchez, Jr

Christophe J Chevallier

Darrell Rinerson

Wayne I Kinney

Edmond R Ward

Philip Swab

Steven W Longcor

Steve Kuo-Ren Hsia

Lawrence Schloss

Roy Lambertson

Christy Mei-Chu Woo

Minh Van Ngo

Steven C Avanzino

Paul Raymond Besser

Suzette Keefe Pangrle

Amit P Marathe

Pin-Chin Connie Wang

Darin A Chan

David Eric Peters

Ramez Nachman

Christine Hau-Riege

Mohammed Aftab Alam

Philip F S Swab

Lawerence Schloss

A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric filed to cause oxygen ionic motion.

Two-terminal reversibly switchable memory device

A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric field effective to cause oxygen ionic motion.

Techniques are described to determine a thickness of individual layers of a plurality of metal layers that include a first metal layer disposed on a polymer material and a second metal layer disposed on the first layer, such that the first layer is between the polymer material and the second layer. A measurement device may determine a resistance of the plurality of metal layers and calculate (e.g., estimate) a thickness of the individual layers based on the resistance of the individual layers and based on a resistivity of individual metals used in the plurality of metal layers. The measurement device may determine whether the individual thicknesses are within predetermined thickness ranges to determine whether to pass a quality control test.

Determining a thickness of individual layers of a plurality of metal layers

A memory cell including conductive oxide electrodes is disclosed. The memory cell includes a memory element operative to store data as a plurality of resistive states. The memory element includes a layer of a conductive metal oxide (CMO) (e.g., a perovskite) in contact with an electrode that may comprise one or more layers of material. At least one of those layers of material can be a conductive oxide (e.g., a perovskite such as LaSrCoO&#x2014;LSCoO or LaNiO&#x2014;LNO) that is in contact with the CMO. The conductive oxide layer can be selected as a seed layer operative to provide a good lattice match with and/or a lower crystallization temperature for the CMO. The conductive oxide layer may also be in contact with a metal layer (e.g., Pt). The memory cell additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays, such as non-volatile two-terminal cross-point memory arrays.

Memory element with a reactive metal layer

A treated conductive element is provided. A conductive element can be treated by depositing either a reactive metal or a very thin layer of material on the conductive element. The reactive metal (or very thin layer of material) would typically be sandwiched between the conductive element and an electrode. The structure additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays.

Method for fabricating multi-resistive state memory devices

A memory cell including conductive oxide electrodes is disclosed. The memory cell includes a memory element operative to store data as a plurality of resistive states. The memory element includes a layer of a conductive metal oxide (CMO) (e.g., a perovskite) in contact with an electrode that may comprise one or more layers of material. At least one of those layers of material can be a conductive oxide (e.g., a perovskite such as LaSrCoO-LSCoO or LaNiO-LNO) that is in contact with the CMO. The conductive oxide layer can be selected as a seed layer operative to provide a good lattice match with and/or a lower crystallization temperature for the CMO. The conductive oxide layer may also be in contact with a metal layer (e.g., Pt). The memory cell additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays, such as non-volatile two-terminal cross-point memory arrays.

Multi-resistive state memory device with conductive oxide electrodes

A movable terminal in a two terminal memory array. A storage medium is disposed between two terminals, one of the terminals being movable relative to the second terminal. Either one of the terminals or both terminals might actually move, resulting in one terminal being moved relative to the other terminal. A memory element disposed between the two terminals has a conductance that is responsive to a write voltage across the electrodes.

Movable terminal in a two terminal memory array

Multi-resistive state element with reactive metal

A multi-resistive state element that uses a treated interface is provided. A memory plug includes at least two electrodes that sandwich a multi-resistive state element. Using different treatments on both electrode/multi-resistive state element interfaces improves the memory properties of the entire memory device.

Resistive memory device with a treated interface

Growing community of inventors

Palo Alto, CA, United States of America

John Espinoza Sanchez, Jr