Koninklijke Philips Corporation N.v.

Philips Electronics North America Corporation

John Edward Dean

Peter J Janssen

Lucian Remus Albu

Jeffrey Arthur Shimizu

Peter J M Janssen

Alok Govil

Jean-Luc Francois-Marie Robert

Douglas Allen Stanton

Franciscus Hendrikus Van Heesch

Shougang Wang

Gerardus Henricus Maria Gijsbers

Viktor L Gornstein

Evgeniy Leyvi

Hong Liu

Remus Albu

Gene Turkenich

Systems, methods, and apparatuses for reducing or eliminating reverberation artifacts in images are disclosed. Systems including one or more ultrasound probes are disclosed. Apparatuses for providing registration information for an ultrasound probe or probes at different positions are disclosed. A method of combining volume images acquired at different positions to reduce or eliminate reverberation artifacts is disclosed.

Systems, methods, and apparatuses for image artifact cancellation

A method and system communicates payload data over a plurality of low voltage differential signaling (LVDS) channels (). First device () transmits the payload data and synchronization information to the second device () over N LVDS channels (), along with a word clock synchronized to the payload data. The second device generates M LVDS receive clocks from the word clock, each having a same frequency that is P times a frequency of the word clock, and each having a different phase. Each of N LVDS receivers () of the second device (): correlates the synchronization data with a reference word using each of the M LVDS receive clocks to produce a correlation value for each of the M LVDS receive clocks; selects a selected LVDS receive clock producing a greatest correlation value; and receives the payload data for the corresponding LVDS channel () using the selected LVDS receive clock.

Method and apparatus for high speed LVDS communication

A method of increasing image dynamic range by breaking each pixel into two or more time displaced samples that are presented to the display in synchronization with appropriate illumination.

Temporal dithering to increase dynamic range of images in sequentially illuminated displays

A color re-mapping method for a sequential display system corrects for slow temporal display response.

Color re-mapping for color sequential displays

A column driver system and method for driving a plurality of column drivers in an active matrix display. The system comprises: a register in each column driver for holding a pixel value; a system that generates a shared ramp signal for the plurality of column drivers; a system that samples the shared ramp signal for each possible pixel value; and a load characteristic correction system that adaptively adjusts the shared ramp signal in anticipation of a load error associated with at least one pixel value. The load characteristic correction system comprises: a data collection system that collects pixel data for each of the plurality of column drivers and determines a number of occurrences of all possible pixel values; a load analysis system that identifies error conditions based on the number of occurrences; and a signal modification system that determines a correction to the ramp signal when an error condition is identified.

Load adaptive column driver

A system and method for managing memory in display processing circuit for use with a color sequential display. The system comprises: a shared memory; and a storage queue coupled to the shared memory, wherein the storage queue includes: a system for receiving and storing alternating packets of color-specific video data in the storage queue; and a system for separately reading contiguous sets color-specific packets from the storage queue to the shared memory.

Color burst queue for a shared memory controller in a color sequential display system

A uniform phase relation restoration method for a. scrolling color projection system wherein the addressing sequence of an LCD panel is altered to change the sweep rate of any one primary color relative to the other two primary colors to momentarily increase the sweep speed of the one color channel while correspondingly decreasing the sweep speed of the other two color channels.

Variable rate row addressing method

An address generator for a pixel shuffler used in a relective liquid crystal display (RLCD) digital video system, and a pixel shuffler incorporating such an address generator. The address generator includes a small, dual port SRAM 160&times;8, a combinatorial converter having a pair of inputs and an output representing a predetermined relationship of the inputs, a pixel counter with a pair of decoders, a line counter, a computing block for selectively implementing a mirror reflection of the pixel addresses, as well as a plurality of D flip flops and logic elements. The pixel shuffler operates in read-modify-write mode, whereby any address location of memory is read and immediately overwritten with the new data. This permits operation with only one bank of SRAM 320&times;96 rather than the customary two banks for prior art pixel shufflers using the so-called Ping Pong method.

Address generator for video pixel reordering in reflective LCD

A prism is mounted onto a motor without regard to its rotation angle relative to the motor index. Its position is electronically set later after construction of the optical path. A motor controller is used to control the rotation of the prism. This motor controller keeps the prism spinning at a constant velocity and positions the prism phase (rotation angle versus time). A variable offset is used to position the absolute prism rotation as a function of time. The phase may be advanced or delayed by an operator during set up. Each prism has its own phase. The phase of each prism in the system is set so that the illumination pattern correctly matches the video addressing of the panel. This is a one time set up during construction. The correct positions are set, and stored in non-volatile memory for life.

Alignment of the optical and the electrical scan in a scrolling color projector

In an electro-optic display device, such as a liquid crystal display device which serves as a modulator for projected light, a global DAC controlled ramp generator is used in conjunction with track and hold circuit for each column of the display to convert incoming digital display signals to analog signals for all columns. Row address circuitry addresses each row of the display, thereby to address the individual pixels of the display device with such analog signals. The limitation on an increase in frame rate, resulting from the finite conversion time (cycle time) of the DAC, is overcome by reducing the grey scale resolution, thus reducing the number of times that the DAC must convert a digital number to an analog voltage during each ramp cycle, and restoring the original resolution using temporal &ldquo;dithering&rdquo;&mdash;i.e., interpolation between the brightness levels of pixels in successive frames.

Apparatus having a DAC-controlled ramp generator for applying voltages to individual pixels in a color electro-optic display device

In an electro-optic display device, such as a liquid crystal display device which serves as a modulator for projected light, a global ramp generator is used in conjunction with track and hold circuits to convert incoming digital display signals to analog signals, and to address the individual pixels of the display device with such analog signals. A plurality of column drivers, each coupled to the ramp generator and to the pixels in a column of the display device, track and hold the ramp voltage signal when it reaches a value corresponding to the desired brightness level of a particular pixel in the respective column. At least one current source is provided, coupled to the signal source output, for supplying current to the signal source output, as needed, to compensate for switching the capacitive load of the column drivers on and off. As a result, transient voltages in the ramp signal are avoided.

Apparatus for applying voltages to individual columns of pixels in a color electro-optic display device

A circuit that is easily configured to convert from a progressive scan image, e.g., at a resolution of 1280.times.720, to an interlaced image scan, e.g., at an interlaced resolution of 1920.times.1080 (1920.times.540 per field), or visa-versa. One arrangement of the circuit employs multiplexers so that the two conversion modes share the available hardware. The circuit is only marginally more complex than a circuit that can only do the conversion in one direction. The quality of the progressive-to-interlace conversion is acceptable for high-end interlaced display systems and the quality of the interlace-to-progressive conversion is at least high enough for 'mid-range' progressive display systems.

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Stormville, NY, United States of America

John Edward Dean