USA as Represented by Secretary of the Navy

Other

Government of the United States

John E Davey

Aristos Christou

Harry B Dietrich

Gordon W Anderson

Howard L Grant

A method of making a self-aligned FET includes the following steps. First, selectively doped heterostructure substrate having a predetermined crystalline structure is obtained having a heavily doped top GaAs layer, having a heavily doped AlGaAs layer under the top layer that is resistant to orientation-dependent etching, and having an undoped underlying AlGaAs layer and an undoped bottom GaAs layer. Then, an uppermost GaAs layer is deposited on the top layer. Then, an angular recess is etched through the uppermost GaAs layer and through the top heavily doped GaAs layer of the heterostructure substrate with an orientation-dependent etchant down to the etch resistant AlGaAs layer, whereby the length of the angular recess is wider at the base of the recess than at the top of the recess because of the predetermined crystalline structure and the orientation-dependent etchant. Next, a refractory metal gate of tantalum silicide is deposited in the recess. The length of the refractory metal gate is substantially the same as the length of the top of the recess and is aligned therewith. The refractory metal gate is then covered with an etch resistant polyimide material. By subsequent steps including etching, source and drain implantation, and deposition of metal contacts, the fabrication of the self-aligned FET is completed.

Method of making self-aligned GaAs/AlGaAs FET's

A self-aligned GaAs FET with an active channel which is unaffected by sure charge trapping/emission. The device comprises a channel of n-doped GaAs, a source and drain regions of n.sup.+ GaAs disposed at opposite ends of the channel, a semi-insulating GaAs layer disposed over the channel, with this GaAs layer having open first and second end surfaces disposed at an angle of greater than or equal to 45.degree. relative to the channel plane. A cavity is disposed in the GaAs layer exposing a portion of the channel, and a gate metallization is disposed over the GaAs layer and extending from the first end surface to the second end surface of the GaAs layer and directly contacting the exposed portion of the channel region in the cavity to form a Schottky barrier contact. This gate metallization is not disposed in contact with a significant portion of either of the first and second end surfaces. The ends of the gate metallization overhang slightly the end surfaces of the GaAs layer in order to provide masking to maintain the first and second end surfaces open during fabrication. An insulator such as air may be disposed in contact with these end surfaces.

Self-aligned gaas fet with low 1/f noise

A TUNNETT (tunneling transit time) electronic device comprising a very thin injector uniformly doped at a high concentration, a thin drift region of lower doping of the same semiconductivity type, and a collector of high doping of the same semiconductivity type. A Schottky barrier is formed by placing a metal electrode on the injector and an ohmic contact may be made on the collector. In a preferred embodiment the injector is made of Ge grown on the drift region by vacuum epitaxy. The drift region is preferably GaAs grown by epitaxy on a GaAs collector.

Tunnett diode and method of making

A method of attaining n.sup.+ regions with fine planar geometry in the soe and drain of GaAs devices utilizing ion implantation which improves ohmic contact with a refractory film. A layer of TiW refractory film is deposited on GaAs. .sup.29 Si ions are implanted in the GaAs through the refractory film so that the peak concentration is no more than approximately 100A below the TiW-GaAs interface. The entire structure is then annealed. A gold overlay is then deposited on the TiW layer to which electrical contacts may be attached and by which the contact resistivity is measured. Typical specific contact resistivity values are in the low 10.sup.-6 ohm/cm.sup.2 range.

Refractory passivated ion-implanted GaAs ohmic contacts

A high-frequency (9.3 GH.sub.z -94 GH.sub.z) gallium arsenide (GaAs) mixer iode having a low Schottky barrier height (approximately 0.4 eV) for operating at low noise figure levels at low local oscillator power levels (0.25 mW -0.75 mW), includes a GaAs substrate, a thin (about 100 A) epitaxial layer of germanium on the substrate, the epitaxial germanium being deposited at a rate of about 6 A per minute and at a substrate temperature in the range of 325.degree. C.-425.degree. C., a layer of silicon dioxide (SiO.sub.2), the SiO.sub.2 being etched, and layers of platinum-titanium-molybdenum-gold on the growth of epitaxial germanium. Contact areas are then plated with a layer of gold. Ohmic contact to the GaAs substrate side includes a deposition of gold-germanium alloy. Each of the layers are individually deposited at certain temperatures and thicknesses in a vacuum.

Low-barrier-height epitaxial Ge-GaAs mixer diode

A method of forming a single, reliable n.sup.+ contact for discrete GaAs devices. A film of p-type Ge is deposited uniformly over the surface of a n-type GaAs substrate. Ions of phosphorous or arsenic are implanted to 5.times.10.sup.18 ions/cc at a depth of 1500 A. The ends and the sides of the substrate and Ge layer are capped by a CVD oxide and annealed at 450.degree.-500.degree. C. for about one hour. This process over-compensates the initial p-type layers which results in the Ge layer becoming n.sup.+. The oxide is removed by an etch process and the n.sup.+ Ge is etched to form two separate contact sections of n.sup.+ Ge. The n.sup.+ Ge is then metalized to form ohmic contacts by use of NiAu. A CVD oxide overcoat may again be applied and annealed at about 500.degree. C. to drive a shallow 200-500 A, n.sup.+ germanium diffusion into the substrate.

Ion-implanted evaporated germanium layers as n.sup.+  contacts to GaAs

A method for protecting an ion-implanted substrate during the annealing process by covering the ion-implanted layer with a suitable encapsulant. A thin layer of ions are implanted into a GaAs substrate. A protective layer of germanium, amorphous GaAs, doped GaAs, or GaAlAs is applied over the implanted layer and on the periphery of the ion-implanted GaAs substrate. The composite is annealed at a temperature which is adequate for the lattice to recover from the ion-implantation-induced damage. The protective layer is removed subsequent to the anneal step, without any damage to the ion-implanted layer.

Semiconductor encapsulant for annealing ion-implanted GaAs

A method of attaining n.sup.+ regions with fine planar geometry in the source and drain of GaAs devices utilizing ion implantation which improves Ohmic contact with a refractory film. A layer of TiW refractory film is deposited on GaAs. .sup.29 Si ions are implanted in the GaAs through the refractory film so that the peak concentration is no more than approximately 100 A below the TiW-GaAs interface. The entire structure is then annealed. A gold overlay is then deposited on the TiW layer to which electrical contacts may be attached and by which the contact resistivity is measured. Typical specific contact resistivity values are in the low 10.sup.-6 ohm/cm.sup.2 range.

Ion-implanted, improved ohmic contacts for GaAs semiconductor devices

A method of growing high-quality, super-abrupt, thin-film epitaxial layers independent of a GaAs substrate. An elemental semiconductor of germanium is used to initiate growth of an active material, typically doped n-type. A semi-insulating layer or n+ layer is grown on the n-type active material. Subsequent to growth of the semi-insulating layer, a thin cap of germanium is deposited on the composite. Gold is deposited onto the germanium cap to form an eutectic-alloy layer with the germanium. The alloy is formed and the composite is bonded to a metal, glass, or ceramic substrate and the semiconductor (germanium) is removed by etching and the n-layer is finally etched to provide a clean-up and to tailor the layer to a desired thickness. Subsequent steps are employed to form desired structures such as field-effect transistors or Schottky-barrier devices.

Method for epitaxial growth of GaAs films and devices configuration

A solid-state diffusion method for providing ohmic contacts to n-type Group II-V semiconductor materials, such as gallium arsenide (GaAs). The material is successively cleaned, etched, rinsed, re-etched, rinsed and placed in an oil-free vacuum. The substrate is then heated to desorb surface oxides and an epitaxial layer of germanium and a layer of nickel, or other refractory, are deposited on the substrate at specific temperatures. Next, the structure is annealed in the vacuum at temperatures sufficient to diffuse the germanium into the GaAs material and to establish an ohmic contact.

Ohmic contacts for group III-V n-type semiconductors using epitaxial

Stress free films of metals, semi-conductors and insulators which have a very uniform thickness and composition and which are supported independent of a substrate, and the method of forming same. Such films have wide application for reflection of light as mirrors and transmission or absorption of light in the form of filters throughout the complete optical spectrum. Also, such films may be used for the study of fundamental properties of the material in question.

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Alexandria, VA, United States of America

John E Davey